0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra USB PHY
0008
0009 maintainers:
0010 - Dmitry Osipenko <digetx@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012 - Thierry Reding <thierry.reding@gmail.com>
0013
0014 properties:
0015 compatible:
0016 oneOf:
0017 - items:
0018 - enum:
0019 - nvidia,tegra124-usb-phy
0020 - nvidia,tegra114-usb-phy
0021 - enum:
0022 - nvidia,tegra30-usb-phy
0023 - items:
0024 - enum:
0025 - nvidia,tegra30-usb-phy
0026 - nvidia,tegra20-usb-phy
0027
0028 reg:
0029 minItems: 1
0030 maxItems: 2
0031 description: |
0032 PHY0 and PHY2 share power and ground, PHY0 contains shared registers.
0033 PHY0 and PHY2 must specify two register sets, where the first set is
0034 PHY own registers and the second set is the PHY0 registers.
0035
0036 clocks:
0037 anyOf:
0038 - items:
0039 - description: Registers clock
0040 - description: Main PHY clock
0041
0042 - items:
0043 - description: Registers clock
0044 - description: Main PHY clock
0045 - description: ULPI PHY clock
0046
0047 - items:
0048 - description: Registers clock
0049 - description: Main PHY clock
0050 - description: UTMI pads control registers clock
0051
0052 - items:
0053 - description: Registers clock
0054 - description: Main PHY clock
0055 - description: UTMI timeout clock
0056 - description: UTMI pads control registers clock
0057
0058 clock-names:
0059 oneOf:
0060 - items:
0061 - const: reg
0062 - const: pll_u
0063
0064 - items:
0065 - const: reg
0066 - const: pll_u
0067 - const: ulpi-link
0068
0069 - items:
0070 - const: reg
0071 - const: pll_u
0072 - const: utmi-pads
0073
0074 - items:
0075 - const: reg
0076 - const: pll_u
0077 - const: timer
0078 - const: utmi-pads
0079
0080 interrupts:
0081 maxItems: 1
0082
0083 resets:
0084 oneOf:
0085 - maxItems: 1
0086 description: PHY reset
0087
0088 - items:
0089 - description: PHY reset
0090 - description: UTMI pads reset
0091
0092 reset-names:
0093 oneOf:
0094 - const: usb
0095
0096 - items:
0097 - const: usb
0098 - const: utmi-pads
0099
0100 "#phy-cells":
0101 const: 0
0102
0103 phy_type:
0104 $ref: /schemas/types.yaml#/definitions/string
0105 enum: [utmi, ulpi, hsic]
0106
0107 dr_mode:
0108 $ref: /schemas/types.yaml#/definitions/string
0109 enum: [host, peripheral, otg]
0110 default: host
0111
0112 vbus-supply:
0113 description: Regulator controlling USB VBUS.
0114
0115 nvidia,has-legacy-mode:
0116 description: |
0117 Indicates whether this controller can operate in legacy mode
0118 (as APX 2500 / 2600). In legacy mode some registers are accessed
0119 through the APB_MISC base address instead of the USB controller.
0120 type: boolean
0121
0122 nvidia,is-wired:
0123 description: |
0124 Indicates whether we can do certain kind of power optimizations for
0125 the devices that are always connected. e.g. modem.
0126 type: boolean
0127
0128 nvidia,has-utmi-pad-registers:
0129 description: |
0130 Indicates whether this controller contains the UTMI pad control
0131 registers common to all USB controllers.
0132 type: boolean
0133
0134 nvidia,hssync-start-delay:
0135 $ref: /schemas/types.yaml#/definitions/uint32
0136 minimum: 0
0137 maximum: 31
0138 description: |
0139 Number of 480 MHz clock cycles to wait before start of sync launches
0140 RxActive.
0141
0142 nvidia,elastic-limit:
0143 $ref: /schemas/types.yaml#/definitions/uint32
0144 minimum: 0
0145 maximum: 31
0146 description: Variable FIFO Depth of elastic input store.
0147
0148 nvidia,idle-wait-delay:
0149 $ref: /schemas/types.yaml#/definitions/uint32
0150 minimum: 0
0151 maximum: 31
0152 description: |
0153 Number of 480 MHz clock cycles of idle to wait before declare IDLE.
0154
0155 nvidia,term-range-adj:
0156 $ref: /schemas/types.yaml#/definitions/uint32
0157 minimum: 0
0158 maximum: 15
0159 description: Range adjustment on terminations.
0160
0161 nvidia,xcvr-setup:
0162 $ref: /schemas/types.yaml#/definitions/uint32
0163 minimum: 0
0164 maximum: 127
0165 description: Input of XCVR cell, HS driver output control.
0166
0167 nvidia,xcvr-setup-use-fuses:
0168 description: Indicates that the value is read from the on-chip fuses.
0169 type: boolean
0170
0171 nvidia,xcvr-lsfslew:
0172 $ref: /schemas/types.yaml#/definitions/uint32
0173 minimum: 0
0174 maximum: 3
0175 description: LS falling slew rate control.
0176
0177 nvidia,xcvr-lsrslew:
0178 $ref: /schemas/types.yaml#/definitions/uint32
0179 minimum: 0
0180 maximum: 3
0181 description: LS rising slew rate control.
0182
0183 nvidia,xcvr-hsslew:
0184 $ref: /schemas/types.yaml#/definitions/uint32
0185 minimum: 0
0186 maximum: 511
0187 description: HS slew rate control.
0188
0189 nvidia,hssquelch-level:
0190 $ref: /schemas/types.yaml#/definitions/uint32
0191 minimum: 0
0192 maximum: 3
0193 description: HS squelch detector level.
0194
0195 nvidia,hsdiscon-level:
0196 $ref: /schemas/types.yaml#/definitions/uint32
0197 minimum: 0
0198 maximum: 7
0199 description: HS disconnect detector level.
0200
0201 nvidia,phy-reset-gpio:
0202 maxItems: 1
0203 description: GPIO used to reset the PHY.
0204
0205 nvidia,pmc:
0206 $ref: /schemas/types.yaml#/definitions/phandle-array
0207 items:
0208 - items:
0209 - description: Phandle to Power Management controller.
0210 - description: USB controller ID.
0211 description:
0212 Phandle to Power Management controller.
0213
0214 required:
0215 - compatible
0216 - reg
0217 - clocks
0218 - clock-names
0219 - resets
0220 - reset-names
0221 - "#phy-cells"
0222 - phy_type
0223
0224 additionalProperties: false
0225
0226 allOf:
0227 - if:
0228 properties:
0229 phy_type:
0230 const: utmi
0231
0232 then:
0233 properties:
0234 reg:
0235 minItems: 2
0236 maxItems: 2
0237
0238 resets:
0239 maxItems: 2
0240
0241 reset-names:
0242 maxItems: 2
0243
0244 required:
0245 - nvidia,hssync-start-delay
0246 - nvidia,elastic-limit
0247 - nvidia,idle-wait-delay
0248 - nvidia,term-range-adj
0249 - nvidia,xcvr-lsfslew
0250 - nvidia,xcvr-lsrslew
0251
0252 anyOf:
0253 - required: ["nvidia,xcvr-setup"]
0254 - required: ["nvidia,xcvr-setup-use-fuses"]
0255
0256 if:
0257 properties:
0258 compatible:
0259 contains:
0260 const: nvidia,tegra30-usb-phy
0261
0262 then:
0263 properties:
0264 clocks:
0265 maxItems: 3
0266
0267 clock-names:
0268 items:
0269 - const: reg
0270 - const: pll_u
0271 - const: utmi-pads
0272
0273 required:
0274 - nvidia,xcvr-hsslew
0275 - nvidia,hssquelch-level
0276 - nvidia,hsdiscon-level
0277
0278 else:
0279 properties:
0280 clocks:
0281 maxItems: 4
0282
0283 clock-names:
0284 items:
0285 - const: reg
0286 - const: pll_u
0287 - const: timer
0288 - const: utmi-pads
0289
0290 - if:
0291 properties:
0292 phy_type:
0293 const: ulpi
0294
0295 then:
0296 properties:
0297 reg:
0298 minItems: 1
0299 maxItems: 1
0300
0301 clocks:
0302 minItems: 2
0303 maxItems: 3
0304
0305 clock-names:
0306 minItems: 2
0307 maxItems: 3
0308
0309 oneOf:
0310 - items:
0311 - const: reg
0312 - const: pll_u
0313
0314 - items:
0315 - const: reg
0316 - const: pll_u
0317 - const: ulpi-link
0318
0319 resets:
0320 minItems: 1
0321 maxItems: 2
0322
0323 reset-names:
0324 minItems: 1
0325 maxItems: 2
0326
0327 examples:
0328 - |
0329 #include <dt-bindings/clock/tegra124-car.h>
0330
0331 usb-phy@7d008000 {
0332 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
0333 reg = <0x7d008000 0x4000>,
0334 <0x7d000000 0x4000>;
0335 interrupts = <0 97 4>;
0336 phy_type = "utmi";
0337 clocks = <&tegra_car TEGRA124_CLK_USB3>,
0338 <&tegra_car TEGRA124_CLK_PLL_U>,
0339 <&tegra_car TEGRA124_CLK_USBD>;
0340 clock-names = "reg", "pll_u", "utmi-pads";
0341 resets = <&tegra_car 59>, <&tegra_car 22>;
0342 reset-names = "usb", "utmi-pads";
0343 #phy-cells = <0>;
0344 nvidia,hssync-start-delay = <0>;
0345 nvidia,idle-wait-delay = <17>;
0346 nvidia,elastic-limit = <16>;
0347 nvidia,term-range-adj = <6>;
0348 nvidia,xcvr-setup = <9>;
0349 nvidia,xcvr-lsfslew = <0>;
0350 nvidia,xcvr-lsrslew = <3>;
0351 nvidia,hssquelch-level = <2>;
0352 nvidia,hsdiscon-level = <5>;
0353 nvidia,xcvr-hsslew = <12>;
0354 nvidia,pmc = <&tegra_pmc 2>;
0355 };
0356
0357 - |
0358 #include <dt-bindings/clock/tegra20-car.h>
0359
0360 usb-phy@c5004000 {
0361 compatible = "nvidia,tegra20-usb-phy";
0362 reg = <0xc5004000 0x4000>;
0363 interrupts = <0 21 4>;
0364 phy_type = "ulpi";
0365 clocks = <&tegra_car TEGRA20_CLK_USB2>,
0366 <&tegra_car TEGRA20_CLK_PLL_U>,
0367 <&tegra_car TEGRA20_CLK_CDEV2>;
0368 clock-names = "reg", "pll_u", "ulpi-link";
0369 resets = <&tegra_car 58>, <&tegra_car 22>;
0370 reset-names = "usb", "utmi-pads";
0371 #phy-cells = <0>;
0372 nvidia,pmc = <&tegra_pmc 1>;
0373 };
