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0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/mixel,mipi-dsi-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006 
0007 title: Mixel DSI PHY for i.MX8
0008 
0009 maintainers:
0010   - Guido Günther <agx@sigxcpu.org>
0011 
0012 description: |
0013   The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
0014   MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
0015   electrical signals for DSI.
0016 
0017   The Mixel PHY IP block found on i.MX8qxp is a combo PHY that can work
0018   in either MIPI-DSI PHY mode or LVDS PHY mode.
0019 
0020 properties:
0021   compatible:
0022     enum:
0023       - fsl,imx8mq-mipi-dphy
0024       - fsl,imx8qxp-mipi-dphy
0025 
0026   reg:
0027     maxItems: 1
0028 
0029   clocks:
0030     maxItems: 1
0031 
0032   clock-names:
0033     const: phy_ref
0034 
0035   assigned-clocks:
0036     maxItems: 1
0037 
0038   assigned-clock-parents:
0039     maxItems: 1
0040 
0041   assigned-clock-rates:
0042     maxItems: 1
0043 
0044   "#phy-cells":
0045     const: 0
0046 
0047   fsl,syscon:
0048     $ref: /schemas/types.yaml#/definitions/phandle
0049     description: |
0050       A phandle which points to Control and Status Registers(CSR) module.
0051 
0052   power-domains:
0053     maxItems: 1
0054 
0055 required:
0056   - compatible
0057   - reg
0058   - clocks
0059   - clock-names
0060   - "#phy-cells"
0061   - power-domains
0062 
0063 allOf:
0064   - if:
0065       properties:
0066         compatible:
0067           contains:
0068             const: fsl,imx8mq-mipi-dphy
0069     then:
0070       properties:
0071         fsl,syscon: false
0072 
0073       required:
0074         - assigned-clocks
0075         - assigned-clock-parents
0076         - assigned-clock-rates
0077 
0078   - if:
0079       properties:
0080         compatible:
0081           contains:
0082             const: fsl,imx8qxp-mipi-dphy
0083     then:
0084       properties:
0085         assigned-clocks: false
0086         assigned-clock-parents: false
0087         assigned-clock-rates: false
0088 
0089       required:
0090         - fsl,syscon
0091 
0092 additionalProperties: false
0093 
0094 examples:
0095   - |
0096     #include <dt-bindings/clock/imx8mq-clock.h>
0097     dphy: dphy@30a0030 {
0098         compatible = "fsl,imx8mq-mipi-dphy";
0099         reg = <0x30a00300 0x100>;
0100         clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
0101         clock-names = "phy_ref";
0102         assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
0103         assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
0104         assigned-clock-rates = <24000000>;
0105         #phy-cells = <0>;
0106         power-domains = <&pgc_mipi>;
0107     };