0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (c) 2020 MediaTek
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/phy/mediatek,xsphy.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: MediaTek XS-PHY Controller Device Tree Bindings
0009
0010 maintainers:
0011 - Chunfeng Yun <chunfeng.yun@mediatek.com>
0012
0013 description: |
0014 The XS-PHY controller supports physical layer functionality for USB3.1
0015 GEN2 controller on MediaTek SoCs.
0016
0017 Banks layout of xsphy
0018 ----------------------------------
0019 port offset bank
0020 u2 port0 0x0000 MISC
0021 0x0100 FMREG
0022 0x0300 U2PHY_COM
0023 u2 port1 0x1000 MISC
0024 0x1100 FMREG
0025 0x1300 U2PHY_COM
0026 u2 port2 0x2000 MISC
0027 ...
0028 u31 common 0x3000 DIG_GLB
0029 0x3100 PHYA_GLB
0030 u31 port0 0x3400 DIG_LN_TOP
0031 0x3500 DIG_LN_TX0
0032 0x3600 DIG_LN_RX0
0033 0x3700 DIG_LN_DAIF
0034 0x3800 PHYA_LN
0035 u31 port1 0x3a00 DIG_LN_TOP
0036 0x3b00 DIG_LN_TX0
0037 0x3c00 DIG_LN_RX0
0038 0x3d00 DIG_LN_DAIF
0039 0x3e00 PHYA_LN
0040 ...
0041 DIG_GLB & PHYA_GLB are shared by U31 ports.
0042
0043 properties:
0044 $nodename:
0045 pattern: "^xs-phy@[0-9a-f]+$"
0046
0047 compatible:
0048 items:
0049 - enum:
0050 - mediatek,mt3611-xsphy
0051 - mediatek,mt3612-xsphy
0052 - const: mediatek,xsphy
0053
0054 reg:
0055 description:
0056 Register shared by multiple U3 ports, exclude port's private register,
0057 if only U2 ports provided, shouldn't use the property.
0058 maxItems: 1
0059
0060 "#address-cells":
0061 enum: [1, 2]
0062
0063 "#size-cells":
0064 enum: [1, 2]
0065
0066 ranges: true
0067
0068 mediatek,src-ref-clk-mhz:
0069 description:
0070 Frequency of reference clock for slew rate calibrate
0071 default: 26
0072
0073 mediatek,src-coef:
0074 description:
0075 Coefficient for slew rate calibrate, depends on SoC process
0076 $ref: /schemas/types.yaml#/definitions/uint32
0077 default: 17
0078
0079 # Required child node:
0080 patternProperties:
0081 "^usb-phy@[0-9a-f]+$":
0082 type: object
0083 description:
0084 A sub-node is required for each port the controller provides.
0085 Address range information including the usual 'reg' property
0086 is used inside these nodes to describe the controller's topology.
0087
0088 properties:
0089 reg:
0090 maxItems: 1
0091
0092 clocks:
0093 items:
0094 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
0095
0096 clock-names:
0097 items:
0098 - const: ref
0099
0100 "#phy-cells":
0101 const: 1
0102 description: |
0103 The cells contain the following arguments.
0104
0105 - description: The PHY type
0106 enum:
0107 - PHY_TYPE_USB2
0108 - PHY_TYPE_USB3
0109
0110 # The following optional vendor properties are only for debug or HQA test
0111 mediatek,eye-src:
0112 description:
0113 The value of slew rate calibrate (U2 phy)
0114 $ref: /schemas/types.yaml#/definitions/uint32
0115 minimum: 1
0116 maximum: 7
0117
0118 mediatek,eye-vrt:
0119 description:
0120 The selection of VRT reference voltage (U2 phy)
0121 $ref: /schemas/types.yaml#/definitions/uint32
0122 minimum: 1
0123 maximum: 7
0124
0125 mediatek,eye-term:
0126 description:
0127 The selection of HS_TX TERM reference voltage (U2 phy)
0128 $ref: /schemas/types.yaml#/definitions/uint32
0129 minimum: 1
0130 maximum: 7
0131
0132 mediatek,efuse-intr:
0133 description:
0134 The selection of Internal Resistor (U2/U3 phy)
0135 $ref: /schemas/types.yaml#/definitions/uint32
0136 minimum: 1
0137 maximum: 63
0138
0139 mediatek,efuse-tx-imp:
0140 description:
0141 The selection of TX Impedance (U3 phy)
0142 $ref: /schemas/types.yaml#/definitions/uint32
0143 minimum: 1
0144 maximum: 31
0145
0146 mediatek,efuse-rx-imp:
0147 description:
0148 The selection of RX Impedance (U3 phy)
0149 $ref: /schemas/types.yaml#/definitions/uint32
0150 minimum: 1
0151 maximum: 31
0152
0153 required:
0154 - reg
0155 - clocks
0156 - clock-names
0157 - "#phy-cells"
0158
0159 additionalProperties: false
0160
0161 required:
0162 - compatible
0163 - "#address-cells"
0164 - "#size-cells"
0165 - ranges
0166
0167 additionalProperties: false
0168
0169 examples:
0170 - |
0171 #include <dt-bindings/phy/phy.h>
0172
0173 u3phy: xs-phy@11c40000 {
0174 compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy";
0175 reg = <0x11c43000 0x0200>;
0176 mediatek,src-ref-clk-mhz = <26>;
0177 mediatek,src-coef = <17>;
0178 #address-cells = <1>;
0179 #size-cells = <1>;
0180 ranges;
0181
0182 u2port0: usb-phy@11c40000 {
0183 reg = <0x11c40000 0x0400>;
0184 clocks = <&clk48m>;
0185 clock-names = "ref";
0186 mediatek,eye-src = <4>;
0187 #phy-cells = <1>;
0188 };
0189
0190 u3port0: usb-phy@11c43000 {
0191 reg = <0x11c43400 0x0500>;
0192 clocks = <&clk26m>;
0193 clock-names = "ref";
0194 mediatek,efuse-intr = <28>;
0195 #phy-cells = <1>;
0196 };
0197 };
0198
0199 ...
