0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (c) 2020 MediaTek
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: MediaTek T-PHY Controller Device Tree Bindings
0009
0010 maintainers:
0011 - Chunfeng Yun <chunfeng.yun@mediatek.com>
0012
0013 description: |
0014 The T-PHY controller supports physical layer functionality for a number of
0015 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
0016
0017 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
0018 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
0019 -----------------------------------
0020 Version 1:
0021 port offset bank
0022 shared 0x0000 SPLLC
0023 0x0100 FMREG
0024 u2 port0 0x0800 U2PHY_COM
0025 u3 port0 0x0900 U3PHYD
0026 0x0a00 U3PHYD_BANK2
0027 0x0b00 U3PHYA
0028 0x0c00 U3PHYA_DA
0029 u2 port1 0x1000 U2PHY_COM
0030 u3 port1 0x1100 U3PHYD
0031 0x1200 U3PHYD_BANK2
0032 0x1300 U3PHYA
0033 0x1400 U3PHYA_DA
0034 u2 port2 0x1800 U2PHY_COM
0035 ...
0036
0037 Version 2/3:
0038 port offset bank
0039 u2 port0 0x0000 MISC
0040 0x0100 FMREG
0041 0x0300 U2PHY_COM
0042 u3 port0 0x0700 SPLLC
0043 0x0800 CHIP
0044 0x0900 U3PHYD
0045 0x0a00 U3PHYD_BANK2
0046 0x0b00 U3PHYA
0047 0x0c00 U3PHYA_DA
0048 u2 port1 0x1000 MISC
0049 0x1100 FMREG
0050 0x1300 U2PHY_COM
0051 u3 port1 0x1700 SPLLC
0052 0x1800 CHIP
0053 0x1900 U3PHYD
0054 0x1a00 U3PHYD_BANK2
0055 0x1b00 U3PHYA
0056 0x1c00 U3PHYA_DA
0057 u2 port2 0x2000 MISC
0058 ...
0059
0060 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
0061 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
0062 added on V2; the FMREG bank for slew rate calibration is not used anymore
0063 and reserved on V3;
0064
0065 properties:
0066 $nodename:
0067 pattern: "^t-phy@[0-9a-f]+$"
0068
0069 compatible:
0070 oneOf:
0071 - items:
0072 - enum:
0073 - mediatek,mt2701-tphy
0074 - mediatek,mt7623-tphy
0075 - mediatek,mt7622-tphy
0076 - mediatek,mt8516-tphy
0077 - const: mediatek,generic-tphy-v1
0078 - items:
0079 - enum:
0080 - mediatek,mt2712-tphy
0081 - mediatek,mt7629-tphy
0082 - mediatek,mt8183-tphy
0083 - mediatek,mt8186-tphy
0084 - mediatek,mt8192-tphy
0085 - mediatek,mt8365-tphy
0086 - const: mediatek,generic-tphy-v2
0087 - items:
0088 - enum:
0089 - mediatek,mt8188-tphy
0090 - mediatek,mt8195-tphy
0091 - const: mediatek,generic-tphy-v3
0092 - const: mediatek,mt2701-u3phy
0093 deprecated: true
0094 - const: mediatek,mt2712-u3phy
0095 deprecated: true
0096 - const: mediatek,mt8173-u3phy
0097
0098 reg:
0099 description:
0100 Register shared by multiple ports, exclude port's private register.
0101 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
0102 T-PHY V2/V3, such as mt2712.
0103 maxItems: 1
0104
0105 "#address-cells":
0106 enum: [1, 2]
0107
0108 "#size-cells":
0109 enum: [1, 2]
0110
0111 # Used with non-empty value if optional 'reg' is not provided.
0112 # The format of the value is an arbitrary number of triplets of
0113 # (child-bus-address, parent-bus-address, length).
0114 ranges: true
0115
0116 mediatek,src-ref-clk-mhz:
0117 description:
0118 Frequency of reference clock for slew rate calibrate
0119 default: 26
0120
0121 mediatek,src-coef:
0122 description:
0123 Coefficient for slew rate calibrate, depends on SoC process
0124 $ref: /schemas/types.yaml#/definitions/uint32
0125 default: 28
0126
0127 # Required child node:
0128 patternProperties:
0129 "^(usb|pcie|sata)-phy@[0-9a-f]+$":
0130 type: object
0131 description:
0132 A sub-node is required for each port the controller provides.
0133 Address range information including the usual 'reg' property
0134 is used inside these nodes to describe the controller's topology.
0135
0136 properties:
0137 reg:
0138 maxItems: 1
0139
0140 clocks:
0141 minItems: 1
0142 items:
0143 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
0144 - description: Reference clock of analog phy
0145 description:
0146 Uses both clocks if the clock of analog and digital phys are
0147 separated, otherwise uses "ref" clock only if needed.
0148
0149 clock-names:
0150 minItems: 1
0151 items:
0152 - const: ref
0153 - const: da_ref
0154
0155 "#phy-cells":
0156 const: 1
0157 description: |
0158 The cells contain the following arguments.
0159
0160 - description: The PHY type
0161 enum:
0162 - PHY_TYPE_USB2
0163 - PHY_TYPE_USB3
0164 - PHY_TYPE_PCIE
0165 - PHY_TYPE_SATA
0166
0167 nvmem-cells:
0168 items:
0169 - description: internal R efuse for U2 PHY or U3/PCIe PHY
0170 - description: rx_imp_sel efuse for U3/PCIe PHY
0171 - description: tx_imp_sel efuse for U3/PCIe PHY
0172 description: |
0173 Phandles to nvmem cell that contains the efuse data;
0174 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
0175 three items should be provided at the same time for U3/PCIe PHY,
0176 when use software to load efuse;
0177 If unspecified, will use hardware auto-load efuse.
0178
0179 nvmem-cell-names:
0180 items:
0181 - const: intr
0182 - const: rx_imp
0183 - const: tx_imp
0184
0185 # The following optional vendor properties are only for debug or HQA test
0186 mediatek,eye-src:
0187 description:
0188 The value of slew rate calibrate (U2 phy)
0189 $ref: /schemas/types.yaml#/definitions/uint32
0190 minimum: 1
0191 maximum: 7
0192
0193 mediatek,eye-vrt:
0194 description:
0195 The selection of VRT reference voltage (U2 phy)
0196 $ref: /schemas/types.yaml#/definitions/uint32
0197 minimum: 1
0198 maximum: 7
0199
0200 mediatek,eye-term:
0201 description:
0202 The selection of HS_TX TERM reference voltage (U2 phy)
0203 $ref: /schemas/types.yaml#/definitions/uint32
0204 minimum: 1
0205 maximum: 7
0206
0207 mediatek,intr:
0208 description:
0209 The selection of internal resistor (U2 phy)
0210 $ref: /schemas/types.yaml#/definitions/uint32
0211 minimum: 1
0212 maximum: 31
0213
0214 mediatek,discth:
0215 description:
0216 The selection of disconnect threshold (U2 phy)
0217 $ref: /schemas/types.yaml#/definitions/uint32
0218 minimum: 1
0219 maximum: 15
0220
0221 mediatek,bc12:
0222 description:
0223 Specify the flag to enable BC1.2 if support it
0224 type: boolean
0225
0226 mediatek,syscon-type:
0227 $ref: /schemas/types.yaml#/definitions/phandle-array
0228 maxItems: 1
0229 description:
0230 A phandle to syscon used to access the register of type switch,
0231 the field should always be 3 cells long.
0232 items:
0233 items:
0234 - description:
0235 The first cell represents a phandle to syscon
0236 - description:
0237 The second cell represents the register offset
0238 - description:
0239 The third cell represents the index of config segment
0240 enum: [0, 1, 2, 3]
0241
0242 required:
0243 - reg
0244 - "#phy-cells"
0245
0246 additionalProperties: false
0247
0248 required:
0249 - compatible
0250 - "#address-cells"
0251 - "#size-cells"
0252 - ranges
0253
0254 additionalProperties: false
0255
0256 examples:
0257 - |
0258 #include <dt-bindings/clock/mt8173-clk.h>
0259 #include <dt-bindings/interrupt-controller/arm-gic.h>
0260 #include <dt-bindings/interrupt-controller/irq.h>
0261 #include <dt-bindings/phy/phy.h>
0262 usb@11271000 {
0263 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
0264 reg = <0x11271000 0x3000>, <0x11280700 0x0100>;
0265 reg-names = "mac", "ippc";
0266 phys = <&u2port0 PHY_TYPE_USB2>,
0267 <&u3port0 PHY_TYPE_USB3>,
0268 <&u2port1 PHY_TYPE_USB2>;
0269 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
0270 clocks = <&topckgen CLK_TOP_USB30_SEL>;
0271 clock-names = "sys_ck";
0272 };
0273
0274 t-phy@11290000 {
0275 compatible = "mediatek,mt8173-u3phy";
0276 reg = <0x11290000 0x800>;
0277 #address-cells = <1>;
0278 #size-cells = <1>;
0279 ranges;
0280
0281 u2port0: usb-phy@11290800 {
0282 reg = <0x11290800 0x100>;
0283 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
0284 clock-names = "ref", "da_ref";
0285 #phy-cells = <1>;
0286 };
0287
0288 u3port0: usb-phy@11290900 {
0289 reg = <0x11290900 0x700>;
0290 clocks = <&clk26m>;
0291 clock-names = "ref";
0292 #phy-cells = <1>;
0293 };
0294
0295 u2port1: usb-phy@11291000 {
0296 reg = <0x11291000 0x100>;
0297 #phy-cells = <1>;
0298 };
0299 };
0300
0301 ...
