0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MediaTek PCIe PHY
0008
0009 maintainers:
0010 - Jianjun Wang <jianjun.wang@mediatek.com>
0011
0012 description: |
0013 The PCIe PHY supports physical layer functionality for PCIe Gen3 port.
0014
0015 properties:
0016 compatible:
0017 const: mediatek,mt8195-pcie-phy
0018
0019 reg:
0020 maxItems: 1
0021
0022 reg-names:
0023 items:
0024 - const: sif
0025
0026 "#phy-cells":
0027 const: 0
0028
0029 nvmem-cells:
0030 maxItems: 7
0031 description:
0032 Phandles to nvmem cell that contains the efuse data, if unspecified,
0033 default value is used.
0034
0035 nvmem-cell-names:
0036 items:
0037 - const: glb_intr
0038 - const: tx_ln0_pmos
0039 - const: tx_ln0_nmos
0040 - const: rx_ln0
0041 - const: tx_ln1_pmos
0042 - const: tx_ln1_nmos
0043 - const: rx_ln1
0044
0045 power-domains:
0046 maxItems: 1
0047
0048 required:
0049 - compatible
0050 - reg
0051 - reg-names
0052 - "#phy-cells"
0053
0054 additionalProperties: false
0055
0056 examples:
0057 - |
0058 phy@11e80000 {
0059 compatible = "mediatek,mt8195-pcie-phy";
0060 #phy-cells = <0>;
0061 reg = <0x11e80000 0x10000>;
0062 reg-names = "sif";
0063 nvmem-cells = <&pciephy_glb_intr>,
0064 <&pciephy_tx_ln0_pmos>,
0065 <&pciephy_tx_ln0_nmos>,
0066 <&pciephy_rx_ln0>,
0067 <&pciephy_tx_ln1_pmos>,
0068 <&pciephy_tx_ln1_nmos>,
0069 <&pciephy_rx_ln1>;
0070 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
0071 "tx_ln0_nmos", "rx_ln0",
0072 "tx_ln1_pmos", "tx_ln1_nmos",
0073 "rx_ln1";
0074 power-domains = <&spm 2>;
0075 };
