0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (c) 2020 MediaTek
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
0009
0010 maintainers:
0011 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
0012 - Philipp Zabel <p.zabel@pengutronix.de>
0013 - Chunfeng Yun <chunfeng.yun@mediatek.com>
0014
0015 description: |
0016 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
0017 output and drives the HDMI pads.
0018
0019 properties:
0020 $nodename:
0021 pattern: "^hdmi-phy@[0-9a-f]+$"
0022
0023 compatible:
0024 oneOf:
0025 - items:
0026 - enum:
0027 - mediatek,mt7623-hdmi-phy
0028 - const: mediatek,mt2701-hdmi-phy
0029 - const: mediatek,mt2701-hdmi-phy
0030 - const: mediatek,mt8173-hdmi-phy
0031
0032 reg:
0033 maxItems: 1
0034
0035 clocks:
0036 items:
0037 - description: PLL reference clock
0038
0039 clock-names:
0040 items:
0041 - const: pll_ref
0042
0043 clock-output-names:
0044 items:
0045 - const: hdmitx_dig_cts
0046
0047 "#phy-cells":
0048 const: 0
0049
0050 "#clock-cells":
0051 const: 0
0052
0053 mediatek,ibias:
0054 description:
0055 TX DRV bias current for < 1.65Gbps
0056 $ref: /schemas/types.yaml#/definitions/uint32
0057 minimum: 0
0058 maximum: 63
0059 default: 0xa
0060
0061 mediatek,ibias_up:
0062 description:
0063 TX DRV bias current for >= 1.65Gbps
0064 $ref: /schemas/types.yaml#/definitions/uint32
0065 minimum: 0
0066 maximum: 63
0067 default: 0x1c
0068
0069 required:
0070 - compatible
0071 - reg
0072 - clocks
0073 - clock-names
0074 - clock-output-names
0075 - "#phy-cells"
0076 - "#clock-cells"
0077
0078 additionalProperties: false
0079
0080 examples:
0081 - |
0082 #include <dt-bindings/clock/mt8173-clk.h>
0083 hdmi_phy: hdmi-phy@10209100 {
0084 compatible = "mediatek,mt8173-hdmi-phy";
0085 reg = <0x10209100 0x24>;
0086 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
0087 clock-names = "pll_ref";
0088 clock-output-names = "hdmitx_dig_cts";
0089 mediatek,ibias = <0xa>;
0090 mediatek,ibias_up = <0x1c>;
0091 #clock-cells = <0>;
0092 #phy-cells = <0>;
0093 };
0094
0095 ...
