0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings
0008
0009 maintainers:
0010 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
0011
0012 properties:
0013 "#phy-cells":
0014 const: 1
0015 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
0016
0017 compatible:
0018 enum:
0019 - lantiq,vrx200-pcie-phy
0020 - lantiq,arx300-pcie-phy
0021
0022 reg:
0023 maxItems: 1
0024
0025 clocks:
0026 items:
0027 - description: PHY module clock
0028 - description: PDI register clock
0029
0030 clock-names:
0031 items:
0032 - const: phy
0033 - const: pdi
0034
0035 resets:
0036 items:
0037 - description: exclusive PHY reset line
0038 - description: shared reset line between the PCIe PHY and PCIe controller
0039
0040 reset-names:
0041 items:
0042 - const: phy
0043 - const: pcie
0044
0045 lantiq,rcu:
0046 $ref: /schemas/types.yaml#/definitions/phandle
0047 description: phandle to the RCU syscon
0048
0049 lantiq,rcu-endian-offset:
0050 $ref: /schemas/types.yaml#/definitions/uint32
0051 description: the offset of the endian registers for this PHY instance in the RCU syscon
0052
0053 lantiq,rcu-big-endian-mask:
0054 $ref: /schemas/types.yaml#/definitions/uint32
0055 description: the mask to set the PDI (PHY) registers for this PHY instance to big endian
0056
0057 big-endian:
0058 description: Configures the PDI (PHY) registers in big-endian mode
0059 type: boolean
0060
0061 little-endian:
0062 description: Configures the PDI (PHY) registers in big-endian mode
0063 type: boolean
0064
0065 required:
0066 - "#phy-cells"
0067 - compatible
0068 - reg
0069 - clocks
0070 - clock-names
0071 - resets
0072 - reset-names
0073 - lantiq,rcu
0074 - lantiq,rcu-endian-offset
0075 - lantiq,rcu-big-endian-mask
0076
0077 additionalProperties: false
0078
0079 examples:
0080 - |
0081 pcie0_phy: phy@106800 {
0082 compatible = "lantiq,vrx200-pcie-phy";
0083 reg = <0x106800 0x100>;
0084 lantiq,rcu = <&rcu0>;
0085 lantiq,rcu-endian-offset = <0x4c>;
0086 lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */
0087 big-endian;
0088 clocks = <&pmu 32>, <&pmu 36>;
0089 clock-names = "phy", "pdi";
0090 resets = <&reset0 12 24>, <&reset0 22 22>;
0091 reset-names = "phy", "pcie";
0092 #phy-cells = <1>;
0093 };
0094
0095 ...
