0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Intel ComboPhy Subsystem
0008
0009 maintainers:
0010 - Dilip Kota <eswara.kota@linux.intel.com>
0011
0012 description: |
0013 Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
0014 controllers. A single Combophy provides two PHY instances.
0015
0016 properties:
0017 $nodename:
0018 pattern: "combophy(@.*|-[0-9a-f])*$"
0019
0020 compatible:
0021 items:
0022 - const: intel,combophy-lgm
0023 - const: intel,combo-phy
0024
0025 clocks:
0026 maxItems: 1
0027
0028 reg:
0029 items:
0030 - description: ComboPhy core registers
0031 - description: PCIe app core control registers
0032
0033 reg-names:
0034 items:
0035 - const: core
0036 - const: app
0037
0038 resets:
0039 maxItems: 4
0040
0041 reset-names:
0042 items:
0043 - const: phy
0044 - const: core
0045 - const: iphy0
0046 - const: iphy1
0047
0048 intel,syscfg:
0049 $ref: /schemas/types.yaml#/definitions/phandle-array
0050 items:
0051 - items:
0052 - description: phandle to Chip configuration registers
0053 - description: ComboPhy instance id
0054 description: Chip configuration registers handle and ComboPhy instance id
0055
0056 intel,hsio:
0057 $ref: /schemas/types.yaml#/definitions/phandle-array
0058 items:
0059 - items:
0060 - description: phandle to HSIO registers
0061 - description: ComboPhy instance id
0062 description: HSIO registers handle and ComboPhy instance id on NOC
0063
0064 intel,aggregation:
0065 type: boolean
0066 description: |
0067 Specify the flag to configure ComboPHY in dual lane mode.
0068
0069 intel,phy-mode:
0070 $ref: /schemas/types.yaml#/definitions/uint32
0071 description: |
0072 Mode of the two phys in ComboPhy.
0073 See dt-bindings/phy/phy.h for values.
0074
0075 "#phy-cells":
0076 const: 1
0077
0078 required:
0079 - compatible
0080 - clocks
0081 - reg
0082 - reg-names
0083 - intel,syscfg
0084 - intel,hsio
0085 - intel,phy-mode
0086 - "#phy-cells"
0087
0088 additionalProperties: false
0089
0090 examples:
0091 - |
0092 #include <dt-bindings/phy/phy.h>
0093 combophy@d0a00000 {
0094 compatible = "intel,combophy-lgm", "intel,combo-phy";
0095 clocks = <&cgu0 1>;
0096 #phy-cells = <1>;
0097 reg = <0xd0a00000 0x40000>,
0098 <0xd0a40000 0x1000>;
0099 reg-names = "core", "app";
0100 resets = <&rcu0 0x50 6>,
0101 <&rcu0 0x50 17>,
0102 <&rcu0 0x50 23>,
0103 <&rcu0 0x50 24>;
0104 reset-names = "phy", "core", "iphy0", "iphy1";
0105 intel,syscfg = <&sysconf 0>;
0106 intel,hsio = <&hsiol 0>;
0107 intel,phy-mode = <PHY_TYPE_PCIE>;
0108 intel,aggregation;
0109 };
