0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-lvds-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Mixel LVDS PHY for Freescale i.MX8qm SoC
0008
0009 maintainers:
0010 - Liu Ying <victor.liu@nxp.com>
0011
0012 description: |
0013 The Mixel LVDS PHY IP block is found on Freescale i.MX8qm SoC.
0014 It converts two groups of four 7/10 bits of CMOS data into two
0015 groups of four data lanes of LVDS data streams. A phase-locked
0016 transmit clock is transmitted in parallel with each group of
0017 data streams over a fifth LVDS link. Every cycle of the transmit
0018 clock, 56/80 bits of input data are sampled and transmitted
0019 through the two groups of LVDS data streams. Together with the
0020 transmit clocks, the two groups of LVDS data streams form two
0021 LVDS channels.
0022
0023 The Mixel LVDS PHY found on Freescale i.MX8qm SoC is controlled
0024 by Control and Status Registers(CSR) module in the SoC. The CSR
0025 module, as a system controller, contains the PHY's registers.
0026
0027 properties:
0028 compatible:
0029 enum:
0030 - fsl,imx8qm-lvds-phy
0031 - mixel,28fdsoi-lvds-1250-8ch-tx-pll
0032
0033 "#phy-cells":
0034 const: 1
0035 description: |
0036 Cell allows setting the LVDS channel index of the PHY.
0037 Index 0 is for LVDS channel0 and index 1 is for LVDS channel1.
0038
0039 clocks:
0040 maxItems: 1
0041
0042 power-domains:
0043 maxItems: 1
0044
0045 required:
0046 - compatible
0047 - "#phy-cells"
0048 - clocks
0049 - power-domains
0050
0051 additionalProperties: false
0052
0053 examples:
0054 - |
0055 #include <dt-bindings/firmware/imx/rsrc.h>
0056 phy {
0057 compatible = "fsl,imx8qm-lvds-phy";
0058 #phy-cells = <1>;
0059 clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_PHY>;
0060 power-domains = <&pd IMX_SC_R_LVDS_0>;
0061 };
