0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings
0008
0009 maintainers:
0010 - Richard Zhu <hongxing.zhu@nxp.com>
0011
0012 properties:
0013 "#phy-cells":
0014 const: 0
0015
0016 compatible:
0017 enum:
0018 - fsl,imx8mm-pcie-phy
0019
0020 reg:
0021 maxItems: 1
0022
0023 clocks:
0024 maxItems: 1
0025
0026 clock-names:
0027 items:
0028 - const: ref
0029
0030 resets:
0031 maxItems: 1
0032
0033 reset-names:
0034 items:
0035 - const: pciephy
0036
0037 fsl,refclk-pad-mode:
0038 description: |
0039 Specifies the mode of the refclk pad used. It can be UNUSED(PHY
0040 refclock is derived from SoC internal source), INPUT(PHY refclock
0041 is provided externally via the refclk pad) or OUTPUT(PHY refclock
0042 is derived from SoC internal source and provided on the refclk pad).
0043 Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
0044 to be used.
0045 $ref: /schemas/types.yaml#/definitions/uint32
0046 enum: [ 0, 1, 2 ]
0047
0048 fsl,tx-deemph-gen1:
0049 description: Gen1 De-emphasis value (optional).
0050 $ref: /schemas/types.yaml#/definitions/uint32
0051 default: 0
0052
0053 fsl,tx-deemph-gen2:
0054 description: Gen2 De-emphasis value (optional).
0055 $ref: /schemas/types.yaml#/definitions/uint32
0056 default: 0
0057
0058 fsl,clkreq-unsupported:
0059 type: boolean
0060 description: A boolean property indicating the CLKREQ# signal is
0061 not supported in the board design (optional)
0062
0063 required:
0064 - "#phy-cells"
0065 - compatible
0066 - reg
0067 - clocks
0068 - clock-names
0069 - fsl,refclk-pad-mode
0070
0071 additionalProperties: false
0072
0073 examples:
0074 - |
0075 #include <dt-bindings/clock/imx8mm-clock.h>
0076 #include <dt-bindings/phy/phy-imx8-pcie.h>
0077 #include <dt-bindings/reset/imx8mq-reset.h>
0078
0079 pcie_phy: pcie-phy@32f00000 {
0080 compatible = "fsl,imx8mm-pcie-phy";
0081 reg = <0x32f00000 0x10000>;
0082 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
0083 clock-names = "ref";
0084 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
0085 assigned-clock-rates = <100000000>;
0086 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
0087 resets = <&src IMX8MQ_RESET_PCIEPHY>;
0088 reset-names = "pciephy";
0089 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
0090 #phy-cells = <0>;
0091 };
0092 ...
