0001 # SPDX-License-Identifier: GPL-2.0
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Allwinner V3s USB PHY Device Tree Bindings
0008
0009 maintainers:
0010 - Chen-Yu Tsai <wens@csie.org>
0011 - Maxime Ripard <mripard@kernel.org>
0012
0013 properties:
0014 "#phy-cells":
0015 const: 1
0016
0017 compatible:
0018 const: allwinner,sun8i-v3s-usb-phy
0019
0020 reg:
0021 items:
0022 - description: PHY Control registers
0023 - description: PHY PMU0 registers
0024
0025 reg-names:
0026 items:
0027 - const: phy_ctrl
0028 - const: pmu0
0029
0030 clocks:
0031 maxItems: 1
0032 description: USB OTG PHY bus clock
0033
0034 clock-names:
0035 const: usb0_phy
0036
0037 resets:
0038 maxItems: 1
0039 description: USB OTG reset
0040
0041 reset-names:
0042 const: usb0_reset
0043
0044 usb0_id_det-gpios:
0045 maxItems: 1
0046 description: GPIO to the USB OTG ID pin
0047
0048 usb0_vbus_det-gpios:
0049 maxItems: 1
0050 description: GPIO to the USB OTG VBUS detect pin
0051
0052 usb0_vbus_power-supply:
0053 description: Power supply to detect the USB OTG VBUS
0054
0055 usb0_vbus-supply:
0056 description: Regulator controlling USB OTG VBUS
0057
0058 required:
0059 - "#phy-cells"
0060 - compatible
0061 - clocks
0062 - clock-names
0063 - reg
0064 - reg-names
0065 - resets
0066 - reset-names
0067
0068 additionalProperties: false
0069
0070 examples:
0071 - |
0072 #include <dt-bindings/gpio/gpio.h>
0073 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
0074 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
0075
0076 phy@1c19400 {
0077 #phy-cells = <1>;
0078 compatible = "allwinner,sun8i-v3s-usb-phy";
0079 reg = <0x01c19400 0x2c>,
0080 <0x01c1a800 0x4>;
0081 reg-names = "phy_ctrl",
0082 "pmu0";
0083 clocks = <&ccu CLK_USB_PHY0>;
0084 clock-names = "usb0_phy";
0085 resets = <&ccu RST_USB_PHY0>;
0086 reset-names = "usb0_reset";
0087 usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
0088 };
