0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/perf/marvell-cn10k-tad.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Marvell CN10K LLC-TAD performance monitor
0008
0009 maintainers:
0010 - Bhaskara Budiredla <bbudiredla@marvell.com>
0011
0012 description: |
0013 The Tag-and-Data units (TADs) maintain coherence and contain CN10K
0014 shared on-chip last level cache (LLC). The tad pmu measures the
0015 performance of last-level cache. Each tad pmu supports up to eight
0016 counters.
0017
0018 The DT setup comprises of number of tad blocks, the sizes of pmu
0019 regions, tad blocks and overall base address of the HW.
0020
0021 properties:
0022 compatible:
0023 const: marvell,cn10k-tad-pmu
0024
0025 reg:
0026 maxItems: 1
0027
0028 marvell,tad-cnt:
0029 description: specifies the number of tads on the soc
0030 $ref: /schemas/types.yaml#/definitions/uint32
0031
0032 marvell,tad-page-size:
0033 description: specifies the size of each tad page
0034 $ref: /schemas/types.yaml#/definitions/uint32
0035
0036 marvell,tad-pmu-page-size:
0037 description: specifies the size of page that the pmu uses
0038 $ref: /schemas/types.yaml#/definitions/uint32
0039
0040 required:
0041 - compatible
0042 - reg
0043 - marvell,tad-cnt
0044 - marvell,tad-page-size
0045 - marvell,tad-pmu-page-size
0046
0047 additionalProperties: false
0048
0049 examples:
0050 - |
0051
0052 tad {
0053 #address-cells = <2>;
0054 #size-cells = <2>;
0055
0056 tad_pmu@80000000 {
0057 compatible = "marvell,cn10k-tad-pmu";
0058 reg = <0x87e2 0x80000000 0x0 0x1000>;
0059 marvell,tad-cnt = <1>;
0060 marvell,tad-page-size = <0x1000>;
0061 marvell,tad-pmu-page-size = <0x1000>;
0062 };
0063 };
