0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/perf/arm,smmu-v3-pmcg.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Arm SMMUv3 Performance Monitor Counter Group
0008
0009 maintainers:
0010 - Will Deacon <will@kernel.org>
0011 - Robin Murphy <robin.murphy@arm.com>
0012
0013 description: |
0014 An SMMUv3 may have several Performance Monitor Counter Group (PMCG).
0015 They are standalone performance monitoring units that support both
0016 architected and IMPLEMENTATION DEFINED event counters.
0017
0018 properties:
0019 $nodename:
0020 pattern: "^pmu@[0-9a-f]*"
0021 compatible:
0022 oneOf:
0023 - items:
0024 - const: arm,mmu-600-pmcg
0025 - const: arm,smmu-v3-pmcg
0026 - const: arm,smmu-v3-pmcg
0027
0028 reg:
0029 items:
0030 - description: Register page 0
0031 - description: Register page 1, if SMMU_PMCG_CFGR.RELOC_CTRS = 1
0032 minItems: 1
0033
0034 interrupts:
0035 maxItems: 1
0036
0037 msi-parent: true
0038
0039 required:
0040 - compatible
0041 - reg
0042
0043 anyOf:
0044 - required:
0045 - interrupts
0046 - required:
0047 - msi-parent
0048
0049 additionalProperties: false
0050
0051 examples:
0052 - |
0053 #include <dt-bindings/interrupt-controller/arm-gic.h>
0054 #include <dt-bindings/interrupt-controller/irq.h>
0055
0056 pmu@2b420000 {
0057 compatible = "arm,smmu-v3-pmcg";
0058 reg = <0x2b420000 0x1000>,
0059 <0x2b430000 0x1000>;
0060 interrupts = <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>;
0061 msi-parent = <&its 0xff0000>;
0062 };
0063
0064 pmu@2b440000 {
0065 compatible = "arm,smmu-v3-pmcg";
0066 reg = <0x2b440000 0x1000>,
0067 <0x2b450000 0x1000>;
0068 interrupts = <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>;
0069 msi-parent = <&its 0xff0000>;
0070 };
