0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright 2021 Arm Ltd.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/perf/arm,dsu-pmu.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
0009
0010 maintainers:
0011 - Suzuki K Poulose <suzuki.poulose@arm.com>
0012 - Robin Murphy <robin.murphy@arm.com>
0013
0014 description:
0015 ARM DynamIQ Shared Unit (DSU) integrates one or more CPU cores with a shared
0016 L3 memory system, control logic and external interfaces to form a multicore
0017 cluster. The PMU enables gathering various statistics on the operation of the
0018 DSU. The PMU provides independent 32-bit counters that can count any of the
0019 supported events, along with a 64-bit cycle counter. The PMU is accessed via
0020 CPU system registers and has no MMIO component.
0021
0022 properties:
0023 compatible:
0024 oneOf:
0025 - const: arm,dsu-pmu
0026 - items:
0027 - const: arm,dsu-110-pmu
0028 - const: arm,dsu-pmu
0029
0030 interrupts:
0031 items:
0032 - description: nCLUSTERPMUIRQ interrupt
0033
0034 cpus:
0035 $ref: /schemas/types.yaml#/definitions/phandle-array
0036 minItems: 1
0037 maxItems: 12
0038 items:
0039 maxItems: 1
0040 description: List of phandles for the CPUs connected to this DSU instance.
0041
0042 required:
0043 - compatible
0044 - interrupts
0045 - cpus
0046
0047 additionalProperties: false
