0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright 2020 Arm Ltd.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/perf/arm,cmn.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Arm CMN (Coherent Mesh Network) Performance Monitors
0009
0010 maintainers:
0011 - Robin Murphy <robin.murphy@arm.com>
0012
0013 properties:
0014 compatible:
0015 enum:
0016 - arm,cmn-600
0017 - arm,cmn-650
0018 - arm,cmn-700
0019 - arm,ci-700
0020
0021 reg:
0022 items:
0023 - description: Physical address of the base (PERIPHBASE) and
0024 size of the configuration address space.
0025
0026 interrupts:
0027 minItems: 1
0028 items:
0029 - description: Overflow interrupt for DTC0
0030 - description: Overflow interrupt for DTC1
0031 - description: Overflow interrupt for DTC2
0032 - description: Overflow interrupt for DTC3
0033 description: One interrupt for each DTC domain implemented must
0034 be specified, in order. DTC0 is always present.
0035
0036 arm,root-node:
0037 $ref: /schemas/types.yaml#/definitions/uint32
0038 description: Offset from PERIPHBASE of CMN-600's configuration
0039 discovery node (see TRM definition of ROOTNODEBASE). Not
0040 relevant for newer CMN/CI products.
0041
0042 required:
0043 - compatible
0044 - reg
0045 - interrupts
0046
0047 if:
0048 properties:
0049 compatible:
0050 contains:
0051 const: arm,cmn-600
0052 then:
0053 required:
0054 - arm,root-node
0055
0056 additionalProperties: false
0057
0058 examples:
0059 - |
0060 #include <dt-bindings/interrupt-controller/arm-gic.h>
0061 #include <dt-bindings/interrupt-controller/irq.h>
0062 pmu@50000000 {
0063 compatible = "arm,cmn-600";
0064 reg = <0x50000000 0x4000000>;
0065 /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */
0066 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
0067 arm,root-node = <0x104000>;
0068 };
0069 ...
