0001 * APM X-Gene SoC PMU bindings
0002
0003 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
0004 The following PMU devices are supported:
0005
0006 L3C - L3 cache controller
0007 IOB - IO bridge
0008 MCB - Memory controller bridge
0009 MC - Memory controller
0010
0011 The following section describes the SoC PMU DT node binding.
0012
0013 Required properties:
0014 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
0015 "apm,xgene-pmu-v2" for revision 2.
0016 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
0017 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
0018 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
0019 - reg : First resource shall be the CPU bus PMU resource.
0020 - interrupts : Interrupt-specifier for PMU IRQ.
0021
0022 Required properties for L3C subnode:
0023 - compatible : Shall be "apm,xgene-pmu-l3c".
0024 - reg : First resource shall be the L3C PMU resource.
0025
0026 Required properties for IOB subnode:
0027 - compatible : Shall be "apm,xgene-pmu-iob".
0028 - reg : First resource shall be the IOB PMU resource.
0029
0030 Required properties for MCB subnode:
0031 - compatible : Shall be "apm,xgene-pmu-mcb".
0032 - reg : First resource shall be the MCB PMU resource.
0033 - enable-bit-index : The bit indicates if the according MCB is enabled.
0034
0035 Required properties for MC subnode:
0036 - compatible : Shall be "apm,xgene-pmu-mc".
0037 - reg : First resource shall be the MC PMU resource.
0038 - enable-bit-index : The bit indicates if the according MC is enabled.
0039
0040 Example:
0041 csw: csw@7e200000 {
0042 compatible = "apm,xgene-csw", "syscon";
0043 reg = <0x0 0x7e200000 0x0 0x1000>;
0044 };
0045
0046 mcba: mcba@7e700000 {
0047 compatible = "apm,xgene-mcb", "syscon";
0048 reg = <0x0 0x7e700000 0x0 0x1000>;
0049 };
0050
0051 mcbb: mcbb@7e720000 {
0052 compatible = "apm,xgene-mcb", "syscon";
0053 reg = <0x0 0x7e720000 0x0 0x1000>;
0054 };
0055
0056 pmu: pmu@78810000 {
0057 compatible = "apm,xgene-pmu-v2";
0058 #address-cells = <2>;
0059 #size-cells = <2>;
0060 ranges;
0061 regmap-csw = <&csw>;
0062 regmap-mcba = <&mcba>;
0063 regmap-mcbb = <&mcbb>;
0064 reg = <0x0 0x78810000 0x0 0x1000>;
0065 interrupts = <0x0 0x22 0x4>;
0066
0067 pmul3c@7e610000 {
0068 compatible = "apm,xgene-pmu-l3c";
0069 reg = <0x0 0x7e610000 0x0 0x1000>;
0070 };
0071
0072 pmuiob@7e940000 {
0073 compatible = "apm,xgene-pmu-iob";
0074 reg = <0x0 0x7e940000 0x0 0x1000>;
0075 };
0076
0077 pmucmcb@7e710000 {
0078 compatible = "apm,xgene-pmu-mcb";
0079 reg = <0x0 0x7e710000 0x0 0x1000>;
0080 enable-bit-index = <0>;
0081 };
0082
0083 pmucmcb@7e730000 {
0084 compatible = "apm,xgene-pmu-mcb";
0085 reg = <0x0 0x7e730000 0x0 0x1000>;
0086 enable-bit-index = <1>;
0087 };
0088
0089 pmucmc@7e810000 {
0090 compatible = "apm,xgene-pmu-mc";
0091 reg = <0x0 0x7e810000 0x0 0x1000>;
0092 enable-bit-index = <0>;
0093 };
0094
0095 pmucmc@7e850000 {
0096 compatible = "apm,xgene-pmu-mc";
0097 reg = <0x0 0x7e850000 0x0 0x1000>;
0098 enable-bit-index = <1>;
0099 };
0100
0101 pmucmc@7e890000 {
0102 compatible = "apm,xgene-pmu-mc";
0103 reg = <0x0 0x7e890000 0x0 0x1000>;
0104 enable-bit-index = <2>;
0105 };
0106
0107 pmucmc@7e8d0000 {
0108 compatible = "apm,xgene-pmu-mc";
0109 reg = <0x0 0x7e8d0000 0x0 0x1000>;
0110 enable-bit-index = <3>;
0111 };
0112 };
