0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: CPM Host Controller device tree for Xilinx Versal SoCs
0008
0009 maintainers:
0010 - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
0011
0012 allOf:
0013 - $ref: /schemas/pci/pci-bus.yaml#
0014
0015 properties:
0016 compatible:
0017 enum:
0018 - xlnx,versal-cpm-host-1.00
0019 - xlnx,versal-cpm5-host
0020
0021 reg:
0022 items:
0023 - description: CPM system level control and status registers.
0024 - description: Configuration space region and bridge registers.
0025 - description: CPM5 control and status registers.
0026 minItems: 2
0027
0028 reg-names:
0029 items:
0030 - const: cpm_slcr
0031 - const: cfg
0032 - const: cpm_csr
0033 minItems: 2
0034
0035 interrupts:
0036 maxItems: 1
0037
0038 msi-map:
0039 description:
0040 Maps a Requester ID to an MSI controller and associated MSI sideband data.
0041
0042 ranges:
0043 maxItems: 2
0044
0045 "#interrupt-cells":
0046 const: 1
0047
0048 interrupt-controller:
0049 description: Interrupt controller node for handling legacy PCI interrupts.
0050 type: object
0051 properties:
0052 "#address-cells":
0053 const: 0
0054 "#interrupt-cells":
0055 const: 1
0056 "interrupt-controller": true
0057 additionalProperties: false
0058
0059 required:
0060 - reg
0061 - reg-names
0062 - "#interrupt-cells"
0063 - interrupts
0064 - interrupt-map
0065 - interrupt-map-mask
0066 - bus-range
0067 - msi-map
0068 - interrupt-controller
0069
0070 unevaluatedProperties: false
0071
0072 examples:
0073 - |
0074
0075 versal {
0076 #address-cells = <2>;
0077 #size-cells = <2>;
0078 cpm_pcie: pcie@fca10000 {
0079 compatible = "xlnx,versal-cpm-host-1.00";
0080 device_type = "pci";
0081 #address-cells = <3>;
0082 #interrupt-cells = <1>;
0083 #size-cells = <2>;
0084 interrupts = <0 72 4>;
0085 interrupt-parent = <&gic>;
0086 interrupt-map-mask = <0 0 0 7>;
0087 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
0088 <0 0 0 2 &pcie_intc_0 1>,
0089 <0 0 0 3 &pcie_intc_0 2>,
0090 <0 0 0 4 &pcie_intc_0 3>;
0091 bus-range = <0x00 0xff>;
0092 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
0093 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
0094 msi-map = <0x0 &its_gic 0x0 0x10000>;
0095 reg = <0x0 0xfca10000 0x0 0x1000>,
0096 <0x6 0x00000000 0x0 0x10000000>;
0097 reg-names = "cpm_slcr", "cfg";
0098 pcie_intc_0: interrupt-controller {
0099 #address-cells = <0>;
0100 #interrupt-cells = <1>;
0101 interrupt-controller;
0102 };
0103 };
0104
0105 cpm5_pcie: pcie@fcdd0000 {
0106 compatible = "xlnx,versal-cpm5-host";
0107 device_type = "pci";
0108 #address-cells = <3>;
0109 #interrupt-cells = <1>;
0110 #size-cells = <2>;
0111 interrupts = <0 72 4>;
0112 interrupt-parent = <&gic>;
0113 interrupt-map-mask = <0 0 0 7>;
0114 interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
0115 <0 0 0 2 &pcie_intc_1 1>,
0116 <0 0 0 3 &pcie_intc_1 2>,
0117 <0 0 0 4 &pcie_intc_1 3>;
0118 bus-range = <0x00 0xff>;
0119 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
0120 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
0121 msi-map = <0x0 &its_gic 0x0 0x10000>;
0122 reg = <0x00 0xfcdd0000 0x00 0x1000>,
0123 <0x06 0x00000000 0x00 0x1000000>,
0124 <0x00 0xfce20000 0x00 0x1000000>;
0125 reg-names = "cpm_slcr", "cfg", "cpm_csr";
0126
0127 pcie_intc_1: interrupt-controller {
0128 #address-cells = <0>;
0129 #interrupt-cells = <1>;
0130 interrupt-controller;
0131 };
0132 };
0133
0134 };
