bindings/pci/xilinx-pcie.txt

0001 * Xilinx AXI PCIe Root Port Bridge DT description
0002
0003 Required properties:
0004 - #address-cells: Address representation for root ports, set to <3>
0005 - #size-cells: Size representation for root ports, set to <2>
0006 - #interrupt-cells: specifies the number of cells needed to encode an
0007         interrupt source. The value must be 1.
0008 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
0009 - reg: Should contain AXI PCIe registers location and length
0010 - device_type: must be "pci"
0011 - interrupts: Should contain AXI PCIe interrupt
0012 - interrupt-map-mask,
0013   interrupt-map: standard PCI properties to define the mapping of the
0014         PCI interface to interrupt numbers.
0015 - ranges: ranges for the PCI memory regions (I/O space region is not
0016         supported by hardware)
0017         Please refer to the standard PCI bus binding document for a more
0018         detailed explanation
0019
0020 Optional properties for Zynq/Microblaze:
0021 - bus-range: PCI bus numbers covered
0022
0023 Interrupt controller child node
0024 +++++++++++++++++++++++++++++++
0025 Required properties:
0026 - interrupt-controller: identifies the node as an interrupt controller
0027 - #address-cells: specifies the number of cells needed to encode an
0028         address. The value must be 0.
0029 - #interrupt-cells: specifies the number of cells needed to encode an
0030         interrupt source. The value must be 1.
0031
0032 NOTE:
0033 The core provides a single interrupt for both INTx/MSI messages. So,
0034 created a interrupt controller node to support 'interrupt-map' DT
0035 functionality.  The driver will create an IRQ domain for this map, decode
0036 the four INTx interrupts in ISR and route them to this domain.
0037
0038
0039 Example:
0040 ++++++++
0041 Zynq:
0042         pci_express: axi-pcie@50000000 {
0043                 #address-cells = <3>;
0044                 #size-cells = <2>;
0045                 #interrupt-cells = <1>;
0046                 compatible = "xlnx,axi-pcie-host-1.00.a";
0047                 reg = < 0x50000000 0x1000000 >;
0048                 device_type = "pci";
0049                 interrupts = < 0 52 4 >;
0050                 interrupt-map-mask = <0 0 0 7>;
0051                 interrupt-map = <0 0 0 1 &pcie_intc 1>,
0052                                 <0 0 0 2 &pcie_intc 2>,
0053                                 <0 0 0 3 &pcie_intc 3>,
0054                                 <0 0 0 4 &pcie_intc 4>;
0055                 ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
0056
0057                 pcie_intc: interrupt-controller {
0058                         interrupt-controller;
0059                         #address-cells = <0>;
0060                         #interrupt-cells = <1>;
0061                 };
0062         };
0063
0064
0065 Microblaze:
0066         pci_express: axi-pcie@10000000 {
0067                 #address-cells = <3>;
0068                 #size-cells = <2>;
0069                 #interrupt-cells = <1>;
0070                 compatible = "xlnx,axi-pcie-host-1.00.a";
0071                 reg = <0x10000000 0x4000000>;
0072                 device_type = "pci";
0073                 interrupt-parent = <&microblaze_0_intc>;
0074                 interrupts = <1 2>;
0075                 interrupt-map-mask = <0 0 0 7>;
0076                 interrupt-map = <0 0 0 1 &pcie_intc 1>,
0077                                 <0 0 0 2 &pcie_intc 2>,
0078                                 <0 0 0 3 &pcie_intc 3>,
0079                                 <0 0 0 4 &pcie_intc 4>;
0080                 ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
0081
0082                 pcie_intc: interrupt-controller {
0083                         interrupt-controller;
0084                         #address-cells = <0>;
0085                         #interrupt-cells = <1>;
0086                 };
0087
0088         };