0001 * Xilinx NWL PCIe Root Port Bridge DT description
0002
0003 Required properties:
0004 - compatible: Should contain "xlnx,nwl-pcie-2.11"
0005 - #address-cells: Address representation for root ports, set to <3>
0006 - #size-cells: Size representation for root ports, set to <2>
0007 - #interrupt-cells: specifies the number of cells needed to encode an
0008 interrupt source. The value must be 1.
0009 - reg: Should contain Bridge, PCIe Controller registers location,
0010 configuration space, and length
0011 - reg-names: Must include the following entries:
0012 "breg": bridge registers
0013 "pcireg": PCIe controller registers
0014 "cfg": configuration space region
0015 - device_type: must be "pci"
0016 - interrupts: Should contain NWL PCIe interrupt
0017 - interrupt-names: Must include the following entries:
0018 "msi1, msi0": interrupt asserted when an MSI is received
0019 "intx": interrupt asserted when a legacy interrupt is received
0020 "misc": interrupt asserted when miscellaneous interrupt is received
0021 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
0022 mapping of the PCI interface to interrupt numbers.
0023 - ranges: ranges for the PCI memory regions (I/O space region is not
0024 supported by hardware)
0025 Please refer to the standard PCI bus binding document for a more
0026 detailed explanation
0027 - msi-controller: indicates that this is MSI controller node
0028 - msi-parent: MSI parent of the root complex itself
0029 - legacy-interrupt-controller: Interrupt controller device node for Legacy
0030 interrupts
0031 - interrupt-controller: identifies the node as an interrupt controller
0032 - #interrupt-cells: should be set to 1
0033 - #address-cells: specifies the number of cells needed to encode an
0034 address. The value must be 0.
0035
0036 Optional properties:
0037 - dma-coherent: present if DMA operations are coherent
0038 - clocks: Input clock specifier. Refer to common clock bindings
0039
0040 Example:
0041 ++++++++
0042
0043 nwl_pcie: pcie@fd0e0000 {
0044 #address-cells = <3>;
0045 #size-cells = <2>;
0046 compatible = "xlnx,nwl-pcie-2.11";
0047 #interrupt-cells = <1>;
0048 msi-controller;
0049 device_type = "pci";
0050 interrupt-parent = <&gic>;
0051 interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
0052 interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
0053 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0054 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
0055 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
0056 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
0057 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
0058
0059 msi-parent = <&nwl_pcie>;
0060 reg = <0x0 0xfd0e0000 0x0 0x1000>,
0061 <0x0 0xfd480000 0x0 0x1000>,
0062 <0x80 0x00000000 0x0 0x1000000>;
0063 reg-names = "breg", "pcireg", "cfg";
0064 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
0065 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
0066
0067 pcie_intc: legacy-interrupt-controller {
0068 interrupt-controller;
0069 #address-cells = <0>;
0070 #interrupt-cells = <1>;
0071 };
0072
0073 };
