0001 * AppliedMicro X-Gene PCIe interface
0002
0003 Required properties:
0004 - device_type: set to "pci"
0005 - compatible: should contain "apm,xgene-pcie" to identify the core.
0006 - reg: A list of physical base address and length for each set of controller
0007 registers. Must contain an entry for each entry in the reg-names
0008 property.
0009 - reg-names: Must include the following entries:
0010 "csr": controller configuration registers.
0011 "cfg": PCIe configuration space registers.
0012 - #address-cells: set to <3>
0013 - #size-cells: set to <2>
0014 - ranges: ranges for the outbound memory, I/O regions.
0015 - dma-ranges: ranges for the inbound memory regions.
0016 - #interrupt-cells: set to <1>
0017 - interrupt-map-mask and interrupt-map: standard PCI properties
0018 to define the mapping of the PCIe interface to interrupt
0019 numbers.
0020 - clocks: from common clock binding: handle to pci clock.
0021
0022 Optional properties:
0023 - status: Either "ok" or "disabled".
0024 - dma-coherent: Present if DMA operations are coherent
0025
0026 Example:
0027
0028 pcie0: pcie@1f2b0000 {
0029 status = "disabled";
0030 device_type = "pci";
0031 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
0032 #interrupt-cells = <1>;
0033 #size-cells = <2>;
0034 #address-cells = <3>;
0035 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
0036 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
0037 reg-names = "csr", "cfg";
0038 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
0039 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
0040 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0041 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
0042 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0043 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
0044 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
0045 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
0046 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
0047 dma-coherent;
0048 clocks = <&pcie0clk 0>;
0049 };
0050
