0001 * AppliedMicro X-Gene v1 PCIe MSI controller
0002
0003 Required properties:
0004
0005 - compatible: should be "apm,xgene1-msi" to identify
0006 X-Gene v1 PCIe MSI controller block.
0007 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
0008 - reg: physical base address (0x79000000) and length (0x900000) for controller
0009 registers. These registers include the MSI termination address and data
0010 registers as well as the MSI interrupt status registers.
0011 - reg-names: not required
0012 - interrupts: A list of 16 interrupt outputs of the controller, starting from
0013 interrupt number 0x10 to 0x1f.
0014 - interrupt-names: not required
0015
0016 Each PCIe node needs to have property msi-parent that points to an MSI
0017 controller node
0018
0019 Examples:
0020
0021 SoC DTSI:
0022
0023 + MSI node:
0024 msi@79000000 {
0025 compatible = "apm,xgene1-msi";
0026 msi-controller;
0027 reg = <0x00 0x79000000 0x0 0x900000>;
0028 interrupts = <0x0 0x10 0x4>
0029 <0x0 0x11 0x4>
0030 <0x0 0x12 0x4>
0031 <0x0 0x13 0x4>
0032 <0x0 0x14 0x4>
0033 <0x0 0x15 0x4>
0034 <0x0 0x16 0x4>
0035 <0x0 0x17 0x4>
0036 <0x0 0x18 0x4>
0037 <0x0 0x19 0x4>
0038 <0x0 0x1a 0x4>
0039 <0x0 0x1b 0x4>
0040 <0x0 0x1c 0x4>
0041 <0x0 0x1d 0x4>
0042 <0x0 0x1e 0x4>
0043 <0x0 0x1f 0x4>;
0044 };
0045
0046 + PCIe controller node with msi-parent property pointing to MSI node:
0047 pcie0: pcie@1f2b0000 {
0048 device_type = "pci";
0049 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
0050 #interrupt-cells = <1>;
0051 #size-cells = <2>;
0052 #address-cells = <3>;
0053 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
0054 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
0055 reg-names = "csr", "cfg";
0056 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
0057 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
0058 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
0059 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
0060 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0061 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
0062 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
0063 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
0064 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>;
0065 dma-coherent;
0066 clocks = <&pcie0clk 0>;
0067 msi-parent= <&msi>;
0068 };
