0001 V3 Semiconductor V360 EPC PCI bridge
0002
0003 This bridge is found in the ARM Integrator/AP (Application Platform)
0004
0005 Required properties:
0006 - compatible: should be one of:
0007 "v3,v360epc-pci"
0008 "arm,integrator-ap-pci", "v3,v360epc-pci"
0009 - reg: should contain two register areas:
0010 first the base address of the V3 host bridge controller, 64KB
0011 second the configuration area register space, 16MB
0012 - interrupts: should contain a reference to the V3 error interrupt
0013 as routed on the system.
0014 - bus-range: see pci.txt
0015 - ranges: this follows the standard PCI bindings in the IEEE Std
0016 1275-1994 (see pci.txt) with the following restriction:
0017 - The non-prefetchable and prefetchable memory windows must
0018 each be exactly 256MB (0x10000000) in size.
0019 - The prefetchable memory window must be immediately adjacent
0020 to the non-prefetcable memory window
0021 - dma-ranges: three ranges for the inbound memory region. The ranges must
0022 be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB,
0023 64MB, 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked
0024 as pre-fetchable. Two ranges are supported by the hardware.
0025
0026 Integrator-specific required properties:
0027 - syscon: should contain a link to the syscon device node, since
0028 on the Integrator, some registers in the syscon are required to
0029 operate the V3 host bridge.
0030
0031 Example:
0032
0033 pci: pciv3@62000000 {
0034 compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
0035 #interrupt-cells = <1>;
0036 #size-cells = <2>;
0037 #address-cells = <3>;
0038 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
0039 interrupt-parent = <&pic>;
0040 interrupts = <17>; /* Bus error IRQ */
0041 clocks = <&pciclk>;
0042 bus-range = <0x00 0xff>;
0043 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
0044 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
0045 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
0046 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
0047 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
0048 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
0049 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
0050 0x20000000 0 0x20000000 /* 512 MB @ LB 20000000 1:1 */
0051 0x02000000 0 0x80000000 /* Core module alias memory */
0052 0x80000000 0 0x40000000>; /* 1GB @ LB 80000000 */
0053 interrupt-map-mask = <0xf800 0 0 0x7>;
0054 interrupt-map = <
0055 /* IDSEL 9 */
0056 0x4800 0 0 1 &pic 13 /* INT A on slot 9 is irq 13 */
0057 0x4800 0 0 2 &pic 14 /* INT B on slot 9 is irq 14 */
0058 0x4800 0 0 3 &pic 15 /* INT C on slot 9 is irq 15 */
0059 0x4800 0 0 4 &pic 16 /* INT D on slot 9 is irq 16 */
0060 /* IDSEL 10 */
0061 0x5000 0 0 1 &pic 14 /* INT A on slot 10 is irq 14 */
0062 0x5000 0 0 2 &pic 15 /* INT B on slot 10 is irq 15 */
0063 0x5000 0 0 3 &pic 16 /* INT C on slot 10 is irq 16 */
0064 0x5000 0 0 4 &pic 13 /* INT D on slot 10 is irq 13 */
0065 /* IDSEL 11 */
0066 0x5800 0 0 1 &pic 15 /* INT A on slot 11 is irq 15 */
0067 0x5800 0 0 2 &pic 16 /* INT B on slot 11 is irq 16 */
0068 0x5800 0 0 3 &pic 13 /* INT C on slot 11 is irq 13 */
0069 0x5800 0 0 4 &pic 14 /* INT D on slot 11 is irq 14 */
0070 /* IDSEL 12 */
0071 0x6000 0 0 1 &pic 16 /* INT A on slot 12 is irq 16 */
0072 0x6000 0 0 2 &pic 13 /* INT B on slot 12 is irq 13 */
0073 0x6000 0 0 3 &pic 14 /* INT C on slot 12 is irq 14 */
0074 0x6000 0 0 4 &pic 15 /* INT D on slot 12 is irq 15 */
0075 >;
0076 };
