0001 TI PCI Controllers
0002
0003 PCIe DesignWare Controller
0004 - compatible: Should be "ti,dra7-pcie" for RC (deprecated)
0005 Should be "ti,dra7-pcie-ep" for EP (deprecated)
0006 Should be "ti,dra746-pcie-rc" for dra74x/dra76 in RC mode
0007 Should be "ti,dra746-pcie-ep" for dra74x/dra76 in EP mode
0008 Should be "ti,dra726-pcie-rc" for dra72x in RC mode
0009 Should be "ti,dra726-pcie-ep" for dra72x in EP mode
0010 - phys : list of PHY specifiers (used by generic PHY framework)
0011 - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
0012 number of PHYs as specified in *phys* property.
0013 - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
0014 where <X> is the instance number of the pcie from the HW spec.
0015 - num-lanes as specified in ../snps,dw-pcie.yaml
0016 - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
0017 module and the register offset to specify lane
0018 selection.
0019
0020 HOST MODE
0021 =========
0022 - reg : Two register ranges as listed in the reg-names property
0023 - reg-names : The first entry must be "ti-conf" for the TI-specific registers
0024 The second entry must be "rc-dbics" for the DesignWare PCIe
0025 registers
0026 The third entry must be "config" for the PCIe configuration space
0027 - interrupts : Two interrupt entries must be specified. The first one is for
0028 main interrupt line and the second for MSI interrupt line.
0029 - #address-cells,
0030 #size-cells,
0031 #interrupt-cells,
0032 device_type,
0033 ranges,
0034 interrupt-map-mask,
0035 interrupt-map : as specified in ../snps,dw-pcie.yaml
0036 - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
0037 should contain the register offset within syscon
0038 and the 2nd argument should contain the bit field
0039 for setting the bit to enable unaligned
0040 access.
0041
0042 DEVICE MODE
0043 ===========
0044 - reg : Four register ranges as listed in the reg-names property
0045 - reg-names : "ti-conf" for the TI-specific registers
0046 "ep_dbics" for the standard configuration registers as
0047 they are locally accessed within the DIF CS space
0048 "ep_dbics2" for the standard configuration registers as
0049 they are locally accessed within the DIF CS2 space
0050 "addr_space" used to map remote RC address space
0051 - interrupts : one interrupt entries must be specified for main interrupt.
0052 - num-ib-windows : number of inbound address translation windows
0053 - num-ob-windows : number of outbound address translation windows
0054 - ti,syscon-unaligned-access: phandle to the syscon DT node. The 1st argument
0055 should contain the register offset within syscon
0056 and the 2nd argument should contain the bit field
0057 for setting the bit to enable unaligned
0058 access.
0059
0060 Optional Property:
0061 - gpios : Should be added if a GPIO line is required to drive PERST# line
0062
0063 NOTE: Two DT nodes may be added for each PCI controller; one for host
0064 mode and another for device mode. So in order for PCI to
0065 work in host mode, EP mode DT node should be disabled and in order to PCI to
0066 work in EP mode, host mode DT node should be disabled. Host mode and EP
0067 mode are mutually exclusive.
0068
0069 Example:
0070 axi {
0071 compatible = "simple-bus";
0072 #size-cells = <1>;
0073 #address-cells = <1>;
0074 ranges = <0x51000000 0x51000000 0x3000
0075 0x0 0x20000000 0x10000000>;
0076 pcie@51000000 {
0077 compatible = "ti,dra7-pcie";
0078 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
0079 reg-names = "rc_dbics", "ti_conf", "config";
0080 interrupts = <0 232 0x4>, <0 233 0x4>;
0081 #address-cells = <3>;
0082 #size-cells = <2>;
0083 device_type = "pci";
0084 ranges = <0x81000000 0 0 0x03000 0 0x00010000
0085 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
0086 #interrupt-cells = <1>;
0087 num-lanes = <1>;
0088 ti,hwmods = "pcie1";
0089 phys = <&pcie1_phy>;
0090 phy-names = "pcie-phy0";
0091 interrupt-map-mask = <0 0 0 7>;
0092 interrupt-map = <0 0 0 1 &pcie_intc 1>,
0093 <0 0 0 2 &pcie_intc 2>,
0094 <0 0 0 3 &pcie_intc 3>,
0095 <0 0 0 4 &pcie_intc 4>;
0096 pcie_intc: interrupt-controller {
0097 interrupt-controller;
0098 #address-cells = <0>;
0099 #interrupt-cells = <1>;
0100 };
0101 };
0102 };
