0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: TI J721E PCI Host (PCIe Wrapper)
0009
0010 maintainers:
0011 - Kishon Vijay Abraham I <kishon@ti.com>
0012
0013 allOf:
0014 - $ref: "cdns-pcie-host.yaml#"
0015
0016 properties:
0017 compatible:
0018 oneOf:
0019 - const: ti,j721e-pcie-host
0020 - description: PCIe controller in AM64
0021 items:
0022 - const: ti,am64-pcie-host
0023 - const: ti,j721e-pcie-host
0024 - description: PCIe controller in J7200
0025 items:
0026 - const: ti,j7200-pcie-host
0027 - const: ti,j721e-pcie-host
0028
0029 reg:
0030 maxItems: 4
0031
0032 reg-names:
0033 items:
0034 - const: intd_cfg
0035 - const: user_cfg
0036 - const: reg
0037 - const: cfg
0038
0039 ti,syscon-pcie-ctrl:
0040 $ref: /schemas/types.yaml#/definitions/phandle-array
0041 items:
0042 - items:
0043 - description: Phandle to the SYSCON entry
0044 - description: pcie_ctrl register offset within SYSCON
0045 description: Specifier for configuring PCIe mode and link speed.
0046
0047 power-domains:
0048 maxItems: 1
0049
0050 clocks:
0051 minItems: 1
0052 maxItems: 2
0053 description: |+
0054 clock-specifier to represent input to the PCIe for 1 item.
0055 2nd item if present represents reference clock to the connector.
0056
0057 clock-names:
0058 minItems: 1
0059 items:
0060 - const: fck
0061 - const: pcie_refclk
0062
0063 dma-coherent: true
0064
0065 vendor-id:
0066 const: 0x104c
0067
0068 device-id:
0069 oneOf:
0070 - items:
0071 - const: 0xb00d
0072 - items:
0073 - const: 0xb00f
0074 - items:
0075 - const: 0xb010
0076
0077 msi-map: true
0078
0079 required:
0080 - compatible
0081 - reg
0082 - reg-names
0083 - ti,syscon-pcie-ctrl
0084 - max-link-speed
0085 - num-lanes
0086 - power-domains
0087 - clocks
0088 - clock-names
0089 - vendor-id
0090 - device-id
0091 - msi-map
0092 - dma-ranges
0093 - ranges
0094 - reset-gpios
0095 - phys
0096 - phy-names
0097
0098 unevaluatedProperties: false
0099
0100 examples:
0101 - |
0102 #include <dt-bindings/soc/ti,sci_pm_domain.h>
0103 #include <dt-bindings/gpio/gpio.h>
0104
0105 bus {
0106 #address-cells = <2>;
0107 #size-cells = <2>;
0108
0109 pcie0_rc: pcie@2900000 {
0110 compatible = "ti,j721e-pcie-host";
0111 reg = <0x00 0x02900000 0x00 0x1000>,
0112 <0x00 0x02907000 0x00 0x400>,
0113 <0x00 0x0d000000 0x00 0x00800000>,
0114 <0x00 0x10000000 0x00 0x00001000>;
0115 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
0116 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
0117 max-link-speed = <3>;
0118 num-lanes = <2>;
0119 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
0120 clocks = <&k3_clks 239 1>;
0121 clock-names = "fck";
0122 device_type = "pci";
0123 #address-cells = <3>;
0124 #size-cells = <2>;
0125 bus-range = <0x0 0xf>;
0126 vendor-id = <0x104c>;
0127 device-id = <0xb00d>;
0128 msi-map = <0x0 &gic_its 0x0 0x10000>;
0129 dma-coherent;
0130 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
0131 phys = <&serdes0_pcie_link>;
0132 phy-names = "pcie-phy";
0133 ranges = <0x01000000 0x0 0x10001000 0x00 0x10001000 0x0 0x0010000>,
0134 <0x02000000 0x0 0x10011000 0x00 0x10011000 0x0 0x7fef000>;
0135 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
0136 };
0137 };
