bindings/pci/ti%2Cj721e-pci-ep.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: TI J721E PCI EP (PCIe Wrapper)
0009
0010 maintainers:
0011   - Kishon Vijay Abraham I <kishon@ti.com>
0012
0013 allOf:
0014   - $ref: "cdns-pcie-ep.yaml#"
0015
0016 properties:
0017   compatible:
0018     oneOf:
0019       - const: ti,j721e-pcie-ep
0020       - description: PCIe EP controller in AM64
0021         items:
0022           - const: ti,am64-pcie-ep
0023           - const: ti,j721e-pcie-ep
0024       - description: PCIe EP controller in J7200
0025         items:
0026           - const: ti,j7200-pcie-ep
0027           - const: ti,j721e-pcie-ep
0028
0029   reg:
0030     maxItems: 4
0031
0032   reg-names:
0033     items:
0034       - const: intd_cfg
0035       - const: user_cfg
0036       - const: reg
0037       - const: mem
0038
0039   ti,syscon-pcie-ctrl:
0040     $ref: /schemas/types.yaml#/definitions/phandle-array
0041     items:
0042       - items:
0043           - description: Phandle to the SYSCON entry
0044           - description: pcie_ctrl register offset within SYSCON
0045     description: Specifier for configuring PCIe mode and link speed.
0046
0047   power-domains:
0048     maxItems: 1
0049
0050   clocks:
0051     maxItems: 1
0052     description: clock-specifier to represent input to the PCIe
0053
0054   clock-names:
0055     items:
0056       - const: fck
0057
0058   dma-coherent:
0059     description: Indicates that the PCIe IP block can ensure the coherency
0060
0061 required:
0062   - compatible
0063   - reg
0064   - reg-names
0065   - ti,syscon-pcie-ctrl
0066   - max-link-speed
0067   - num-lanes
0068   - power-domains
0069   - clocks
0070   - clock-names
0071   - max-functions
0072   - phys
0073   - phy-names
0074
0075 unevaluatedProperties: false
0076
0077 examples:
0078   - |
0079     #include <dt-bindings/soc/ti,sci_pm_domain.h>
0080
0081     bus {
0082         #address-cells = <2>;
0083         #size-cells = <2>;
0084
0085         pcie0_ep: pcie-ep@d000000 {
0086            compatible = "ti,j721e-pcie-ep";
0087            reg = <0x00 0x02900000 0x00 0x1000>,
0088                  <0x00 0x02907000 0x00 0x400>,
0089                  <0x00 0x0d000000 0x00 0x00800000>,
0090                  <0x00 0x10000000 0x00 0x08000000>;
0091            reg-names = "intd_cfg", "user_cfg", "reg", "mem";
0092            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
0093            max-link-speed = <3>;
0094            num-lanes = <2>;
0095            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
0096            clocks = <&k3_clks 239 1>;
0097            clock-names = "fck";
0098            max-functions = /bits/ 8 <6>;
0099            dma-coherent;
0100            phys = <&serdes0_pcie_link>;
0101            phy-names = "pcie-phy";
0102        };
0103     };