0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: TI AM65 PCI Endpoint
0009
0010 maintainers:
0011 - Kishon Vijay Abraham I <kishon@ti.com>
0012
0013 allOf:
0014 - $ref: pci-ep.yaml#
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - ti,am654-pcie-ep
0020
0021 reg:
0022 maxItems: 4
0023
0024 reg-names:
0025 items:
0026 - const: app
0027 - const: dbics
0028 - const: addr_space
0029 - const: atu
0030
0031 power-domains:
0032 maxItems: 1
0033
0034 ti,syscon-pcie-mode:
0035 $ref: /schemas/types.yaml#/definitions/phandle-array
0036 items:
0037 - items:
0038 - description: Phandle to the SYSCON entry
0039 - description: pcie_ctrl register offset within SYSCON
0040 description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
0041
0042 interrupts:
0043 minItems: 1
0044
0045 dma-coherent: true
0046
0047 required:
0048 - compatible
0049 - reg
0050 - reg-names
0051 - max-link-speed
0052 - power-domains
0053 - ti,syscon-pcie-mode
0054 - dma-coherent
0055
0056 unevaluatedProperties: false
0057
0058 examples:
0059 - |
0060 #include <dt-bindings/interrupt-controller/arm-gic.h>
0061 #include <dt-bindings/interrupt-controller/irq.h>
0062 #include <dt-bindings/soc/ti,sci_pm_domain.h>
0063
0064 pcie0_ep: pcie-ep@5500000 {
0065 compatible = "ti,am654-pcie-ep";
0066 reg = <0x5500000 0x1000>,
0067 <0x5501000 0x1000>,
0068 <0x10000000 0x8000000>,
0069 <0x5506000 0x1000>;
0070 reg-names = "app", "dbics", "addr_space", "atu";
0071 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
0072 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
0073 max-link-speed = <2>;
0074 dma-coherent;
0075 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
0076 };
