0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Socionext UniPhier PCIe host controller
0008
0009 description: |
0010 UniPhier PCIe host controller is based on the Synopsys DesignWare
0011 PCI core. It shares common features with the PCIe DesignWare core and
0012 inherits common properties defined in
0013 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
0014
0015 maintainers:
0016 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
0017
0018 allOf:
0019 - $ref: /schemas/pci/snps,dw-pcie.yaml#
0020
0021 properties:
0022 compatible:
0023 enum:
0024 - socionext,uniphier-pcie
0025
0026 reg:
0027 minItems: 3
0028 maxItems: 4
0029
0030 reg-names:
0031 minItems: 3
0032 items:
0033 - const: dbi
0034 - const: link
0035 - const: config
0036 - const: atu
0037
0038 clocks:
0039 maxItems: 1
0040
0041 resets:
0042 maxItems: 1
0043
0044 num-viewport: true
0045
0046 num-lanes: true
0047
0048 phys:
0049 maxItems: 1
0050
0051 phy-names:
0052 const: pcie-phy
0053
0054 interrupt-controller:
0055 type: object
0056 additionalProperties: false
0057
0058 properties:
0059 interrupt-controller: true
0060
0061 '#interrupt-cells':
0062 const: 1
0063
0064 interrupts:
0065 maxItems: 1
0066
0067 required:
0068 - compatible
0069 - reg
0070 - reg-names
0071 - clocks
0072 - resets
0073
0074 unevaluatedProperties: false
0075
0076 examples:
0077 - |
0078 bus {
0079 gic: interrupt-controller {
0080 interrupt-controller;
0081 #interrupt-cells = <3>;
0082 };
0083 };
0084
0085 pcie: pcie@66000000 {
0086 compatible = "socionext,uniphier-pcie";
0087 reg-names = "dbi", "link", "config";
0088 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
0089 #address-cells = <3>;
0090 #size-cells = <2>;
0091 clocks = <&sys_clk 24>;
0092 resets = <&sys_rst 24>;
0093 num-lanes = <1>;
0094 num-viewport = <1>;
0095 bus-range = <0x0 0xff>;
0096 device_type = "pci";
0097 ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
0098 <0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
0099 phy-names = "pcie-phy";
0100 phys = <&pcie_phy>;
0101 #interrupt-cells = <1>;
0102 interrupt-names = "dma", "msi";
0103 interrupt-parent = <&gic>;
0104 interrupts = <0 224 4>, <0 225 4>;
0105 interrupt-map-mask = <0 0 0 7>;
0106 interrupt-map = <0 0 0 1 &pcie_intc 0>,
0107 <0 0 0 2 &pcie_intc 1>,
0108 <0 0 0 3 &pcie_intc 2>,
0109 <0 0 0 4 &pcie_intc 3>;
0110
0111 pcie_intc: interrupt-controller {
0112 interrupt-controller;
0113 #interrupt-cells = <1>;
0114 interrupt-parent = <&gic>;
0115 interrupts = <0 226 4>;
0116 };
0117 };
