0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung SoC series PCIe Host Controller Device Tree Bindings
0008
0009 maintainers:
0010 - Marek Szyprowski <m.szyprowski@samsung.com>
0011 - Jaehoon Chung <jh80.chung@samsung.com>
0012
0013 description: |+
0014 Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare
0015 PCIe IP and thus inherits all the common properties defined in
0016 snps,dw-pcie.yaml.
0017
0018 allOf:
0019 - $ref: /schemas/pci/snps,dw-pcie.yaml#
0020
0021 properties:
0022 compatible:
0023 const: samsung,exynos5433-pcie
0024
0025 reg:
0026 items:
0027 - description: Data Bus Interface (DBI) registers.
0028 - description: External Local Bus interface (ELBI) registers.
0029 - description: PCIe configuration space region.
0030
0031 reg-names:
0032 items:
0033 - const: dbi
0034 - const: elbi
0035 - const: config
0036
0037 interrupts:
0038 maxItems: 1
0039
0040 clocks:
0041 items:
0042 - description: PCIe bridge clock
0043 - description: PCIe bus clock
0044
0045 clock-names:
0046 items:
0047 - const: pcie
0048 - const: pcie_bus
0049
0050 phys:
0051 maxItems: 1
0052
0053 vdd10-supply:
0054 description:
0055 Phandle to a regulator that provides 1.0V power to the PCIe block.
0056
0057 vdd18-supply:
0058 description:
0059 Phandle to a regulator that provides 1.8V power to the PCIe block.
0060
0061 num-lanes:
0062 const: 1
0063
0064 num-viewport:
0065 const: 3
0066
0067 required:
0068 - reg
0069 - reg-names
0070 - interrupts
0071 - "#address-cells"
0072 - "#size-cells"
0073 - "#interrupt-cells"
0074 - interrupt-map
0075 - interrupt-map-mask
0076 - ranges
0077 - bus-range
0078 - device_type
0079 - num-lanes
0080 - num-viewport
0081 - clocks
0082 - clock-names
0083 - phys
0084 - vdd10-supply
0085 - vdd18-supply
0086
0087 unevaluatedProperties: false
0088
0089 examples:
0090 - |
0091 #include <dt-bindings/interrupt-controller/irq.h>
0092 #include <dt-bindings/interrupt-controller/arm-gic.h>
0093 #include <dt-bindings/clock/exynos5433.h>
0094
0095 pcie: pcie@15700000 {
0096 compatible = "samsung,exynos5433-pcie";
0097 reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;
0098 reg-names = "dbi", "elbi", "config";
0099 #address-cells = <3>;
0100 #size-cells = <2>;
0101 #interrupt-cells = <1>;
0102 device_type = "pci";
0103 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
0104 clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;
0105 clock-names = "pcie", "pcie_bus";
0106 phys = <&pcie_phy>;
0107 pinctrl-0 = <&pcie_bus &pcie_wlanen>;
0108 pinctrl-names = "default";
0109 num-lanes = <1>;
0110 num-viewport = <3>;
0111 bus-range = <0x00 0xff>;
0112 ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
0113 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;
0114 vdd10-supply = <&ldo6_reg>;
0115 vdd18-supply = <&ldo7_reg>;
0116 interrupt-map-mask = <0 0 0 0>;
0117 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
0118 };
0119 ...
