0001 * Rockchip AXI PCIe Root Port Bridge DT description
0002
0003 Required properties:
0004 - #address-cells: Address representation for root ports, set to <3>
0005 - #size-cells: Size representation for root ports, set to <2>
0006 - #interrupt-cells: specifies the number of cells needed to encode an
0007 interrupt source. The value must be 1.
0008 - compatible: Should contain "rockchip,rk3399-pcie"
0009 - reg: Two register ranges as listed in the reg-names property
0010 - reg-names: Must include the following names
0011 - "axi-base"
0012 - "apb-base"
0013 - clocks: Must contain an entry for each entry in clock-names.
0014 See ../clocks/clock-bindings.txt for details.
0015 - clock-names: Must include the following entries:
0016 - "aclk"
0017 - "aclk-perf"
0018 - "hclk"
0019 - "pm"
0020 - msi-map: Maps a Requester ID to an MSI controller and associated
0021 msi-specifier data. See ./pci-msi.txt
0022 - interrupts: Three interrupt entries must be specified.
0023 - interrupt-names: Must include the following names
0024 - "sys"
0025 - "legacy"
0026 - "client"
0027 - resets: Must contain seven entries for each entry in reset-names.
0028 See ../reset/reset.txt for details.
0029 - reset-names: Must include the following names
0030 - "core"
0031 - "mgmt"
0032 - "mgmt-sticky"
0033 - "pipe"
0034 - "pm"
0035 - "aclk"
0036 - "pclk"
0037 - pinctrl-names : The pin control state names
0038 - pinctrl-0: The "default" pinctrl state
0039 - #interrupt-cells: specifies the number of cells needed to encode an
0040 interrupt source. The value must be 1.
0041 - interrupt-map-mask and interrupt-map: standard PCI properties
0042
0043 Required properties for legacy PHY model (deprecated):
0044 - phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
0045 - phy-names: MUST be "pcie-phy".
0046
0047 Required properties for per-lane PHY model (preferred):
0048 - phys: Must contain an phandle to a PHY for each entry in phy-names.
0049 - phy-names: Must include 4 entries for all 4 lanes even if some of
0050 them won't be used for your cases. Entries are of the form "pcie-phy-N":
0051 where N ranges from 0 to 3.
0052 (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
0053 for changing the #phy-cells of phy node to support it)
0054
0055 Optional Property:
0056 - aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
0057 using 24MHz OSC for RC's PHY.
0058 - ep-gpios: contain the entry for pre-reset GPIO
0059 - num-lanes: number of lanes to use
0060 - vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
0061 - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
0062 - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
0063 - vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
0064
0065 *Interrupt controller child node*
0066 The core controller provides a single interrupt for legacy INTx. The PCIe node
0067 should contain an interrupt controller node as a target for the PCI
0068 'interrupt-map' property. This node represents the domain at which the four
0069 INTx interrupts are decoded and routed.
0070
0071
0072 Required properties for Interrupt controller child node:
0073 - interrupt-controller: identifies the node as an interrupt controller
0074 - #address-cells: specifies the number of cells needed to encode an
0075 address. The value must be 0.
0076 - #interrupt-cells: specifies the number of cells needed to encode an
0077 interrupt source. The value must be 1.
0078
0079 Example:
0080
0081 pcie0: pcie@f8000000 {
0082 compatible = "rockchip,rk3399-pcie";
0083 #address-cells = <3>;
0084 #size-cells = <2>;
0085 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
0086 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
0087 clock-names = "aclk", "aclk-perf",
0088 "hclk", "pm";
0089 bus-range = <0x0 0x1>;
0090 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
0091 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
0092 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
0093 interrupt-names = "sys", "legacy", "client";
0094 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
0095 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
0096 assigned-clock-rates = <100000000>;
0097 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
0098 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
0099 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
0100 num-lanes = <4>;
0101 msi-map = <0x0 &its 0x0 0x1000>;
0102 reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
0103 reg-names = "axi-base", "apb-base";
0104 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
0105 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
0106 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
0107 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
0108 "pm", "pclk", "aclk";
0109 /* deprecated legacy PHY model */
0110 phys = <&pcie_phy>;
0111 phy-names = "pcie-phy";
0112 pinctrl-names = "default";
0113 pinctrl-0 = <&pcie_clkreq>;
0114 #interrupt-cells = <1>;
0115 interrupt-map-mask = <0 0 0 7>;
0116 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
0117 <0 0 0 2 &pcie0_intc 1>,
0118 <0 0 0 3 &pcie0_intc 2>,
0119 <0 0 0 4 &pcie0_intc 3>;
0120 pcie0_intc: interrupt-controller {
0121 interrupt-controller;
0122 #address-cells = <0>;
0123 #interrupt-cells = <1>;
0124 };
0125 };
0126
0127 pcie0: pcie@f8000000 {
0128 ...
0129
0130 /* preferred per-lane PHY model */
0131 phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
0132 phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
0133
0134 ...
0135 };
