0001 * Rockchip AXI PCIe Endpoint Controller DT description
0002
0003 Required properties:
0004 - compatible: Should contain "rockchip,rk3399-pcie-ep"
0005 - reg: Two register ranges as listed in the reg-names property
0006 - reg-names: Must include the following names
0007 - "apb-base"
0008 - "mem-base"
0009 - clocks: Must contain an entry for each entry in clock-names.
0010 See ../clocks/clock-bindings.txt for details.
0011 - clock-names: Must include the following entries:
0012 - "aclk"
0013 - "aclk-perf"
0014 - "hclk"
0015 - "pm"
0016 - resets: Must contain seven entries for each entry in reset-names.
0017 See ../reset/reset.txt for details.
0018 - reset-names: Must include the following names
0019 - "core"
0020 - "mgmt"
0021 - "mgmt-sticky"
0022 - "pipe"
0023 - "pm"
0024 - "aclk"
0025 - "pclk"
0026 - pinctrl-names : The pin control state names
0027 - pinctrl-0: The "default" pinctrl state
0028 - phys: Must contain an phandle to a PHY for each entry in phy-names.
0029 - phy-names: Must include 4 entries for all 4 lanes even if some of
0030 them won't be used for your cases. Entries are of the form "pcie-phy-N":
0031 where N ranges from 0 to 3.
0032 (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
0033 for changing the #phy-cells of phy node to support it)
0034 - rockchip,max-outbound-regions: Maximum number of outbound regions
0035
0036 Optional Property:
0037 - num-lanes: number of lanes to use
0038 - max-functions: Maximum number of functions that can be configured (default 1).
0039
0040 pcie0-ep: pcie@f8000000 {
0041 compatible = "rockchip,rk3399-pcie-ep";
0042 #address-cells = <3>;
0043 #size-cells = <2>;
0044 rockchip,max-outbound-regions = <16>;
0045 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
0046 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
0047 clock-names = "aclk", "aclk-perf",
0048 "hclk", "pm";
0049 max-functions = /bits/ 8 <8>;
0050 num-lanes = <4>;
0051 reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
0052 reg-names = "apb-base", "mem-base";
0053 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
0054 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
0055 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
0056 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
0057 "pm", "pclk", "aclk";
0058 phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
0059 phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
0060 pinctrl-names = "default";
0061 pinctrl-0 = <&pcie_clkreq>;
0062 };
