0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: DesignWare based PCIe controller on Rockchip SoCs
0008
0009 maintainers:
0010 - Shawn Lin <shawn.lin@rock-chips.com>
0011 - Simon Xue <xxm@rock-chips.com>
0012 - Heiko Stuebner <heiko@sntech.de>
0013
0014 description: |+
0015 RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
0016 PCIe IP and thus inherits all the common properties defined in
0017 designware-pcie.txt.
0018
0019 allOf:
0020 - $ref: /schemas/pci/pci-bus.yaml#
0021
0022 properties:
0023 compatible:
0024 items:
0025 - const: rockchip,rk3568-pcie
0026
0027 reg:
0028 items:
0029 - description: Data Bus Interface (DBI) registers
0030 - description: Rockchip designed configuration registers
0031 - description: Config registers
0032
0033 reg-names:
0034 items:
0035 - const: dbi
0036 - const: apb
0037 - const: config
0038
0039 clocks:
0040 items:
0041 - description: AHB clock for PCIe master
0042 - description: AHB clock for PCIe slave
0043 - description: AHB clock for PCIe dbi
0044 - description: APB clock for PCIe
0045 - description: Auxiliary clock for PCIe
0046
0047 clock-names:
0048 items:
0049 - const: aclk_mst
0050 - const: aclk_slv
0051 - const: aclk_dbi
0052 - const: pclk
0053 - const: aux
0054
0055 msi-map: true
0056
0057 num-lanes: true
0058
0059 phys:
0060 maxItems: 1
0061
0062 phy-names:
0063 const: pcie-phy
0064
0065 power-domains:
0066 maxItems: 1
0067
0068 ranges:
0069 maxItems: 2
0070
0071 resets:
0072 maxItems: 1
0073
0074 reset-names:
0075 const: pipe
0076
0077 vpcie3v3-supply: true
0078
0079 required:
0080 - compatible
0081 - reg
0082 - reg-names
0083 - clocks
0084 - clock-names
0085 - msi-map
0086 - num-lanes
0087 - phys
0088 - phy-names
0089 - power-domains
0090 - resets
0091 - reset-names
0092
0093 unevaluatedProperties: false
0094
0095 examples:
0096 - |
0097
0098 bus {
0099 #address-cells = <2>;
0100 #size-cells = <2>;
0101
0102 pcie3x2: pcie@fe280000 {
0103 compatible = "rockchip,rk3568-pcie";
0104 reg = <0x3 0xc0800000 0x0 0x390000>,
0105 <0x0 0xfe280000 0x0 0x10000>,
0106 <0x3 0x80000000 0x0 0x100000>;
0107 reg-names = "dbi", "apb", "config";
0108 bus-range = <0x20 0x2f>;
0109 clocks = <&cru 143>, <&cru 144>,
0110 <&cru 145>, <&cru 146>,
0111 <&cru 147>;
0112 clock-names = "aclk_mst", "aclk_slv",
0113 "aclk_dbi", "pclk",
0114 "aux";
0115 device_type = "pci";
0116 linux,pci-domain = <2>;
0117 max-link-speed = <2>;
0118 msi-map = <0x2000 &its 0x2000 0x1000>;
0119 num-lanes = <2>;
0120 phys = <&pcie30phy>;
0121 phy-names = "pcie-phy";
0122 power-domains = <&power 15>;
0123 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
0124 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
0125 resets = <&cru 193>;
0126 reset-names = "pipe";
0127 #address-cells = <3>;
0128 #size-cells = <2>;
0129 };
0130 };
0131 ...
