0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 Renesas Electronics Corp.
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Renesas R-Car PCIe Host
0009
0010 maintainers:
0011 - Marek Vasut <marek.vasut+renesas@gmail.com>
0012 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
0013
0014 allOf:
0015 - $ref: pci-bus.yaml#
0016
0017 properties:
0018 compatible:
0019 oneOf:
0020 - const: renesas,pcie-r8a7779 # R-Car H1
0021 - items:
0022 - enum:
0023 - renesas,pcie-r8a7742 # RZ/G1H
0024 - renesas,pcie-r8a7743 # RZ/G1M
0025 - renesas,pcie-r8a7744 # RZ/G1N
0026 - renesas,pcie-r8a7790 # R-Car H2
0027 - renesas,pcie-r8a7791 # R-Car M2-W
0028 - renesas,pcie-r8a7793 # R-Car M2-N
0029 - const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
0030 - items:
0031 - enum:
0032 - renesas,pcie-r8a774a1 # RZ/G2M
0033 - renesas,pcie-r8a774b1 # RZ/G2N
0034 - renesas,pcie-r8a774c0 # RZ/G2E
0035 - renesas,pcie-r8a774e1 # RZ/G2H
0036 - renesas,pcie-r8a7795 # R-Car H3
0037 - renesas,pcie-r8a7796 # R-Car M3-W
0038 - renesas,pcie-r8a77961 # R-Car M3-W+
0039 - renesas,pcie-r8a77965 # R-Car M3-N
0040 - renesas,pcie-r8a77980 # R-Car V3H
0041 - renesas,pcie-r8a77990 # R-Car E3
0042 - const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
0043
0044 reg:
0045 maxItems: 1
0046
0047 interrupts:
0048 minItems: 3
0049 maxItems: 3
0050
0051 clocks:
0052 maxItems: 2
0053
0054 clock-names:
0055 items:
0056 - const: pcie
0057 - const: pcie_bus
0058
0059 power-domains:
0060 maxItems: 1
0061
0062 resets:
0063 maxItems: 1
0064
0065 phys:
0066 maxItems: 1
0067
0068 phy-names:
0069 const: pcie
0070
0071 required:
0072 - compatible
0073 - reg
0074 - interrupts
0075 - clocks
0076 - clock-names
0077 - power-domains
0078
0079 if:
0080 not:
0081 properties:
0082 compatible:
0083 contains:
0084 const: renesas,pcie-r8a7779
0085 then:
0086 required:
0087 - resets
0088
0089 unevaluatedProperties: false
0090
0091 examples:
0092 - |
0093 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
0094 #include <dt-bindings/interrupt-controller/arm-gic.h>
0095 #include <dt-bindings/power/r8a7791-sysc.h>
0096
0097 soc {
0098 #address-cells = <2>;
0099 #size-cells = <2>;
0100
0101 pcie: pcie@fe000000 {
0102 compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
0103 reg = <0 0xfe000000 0 0x80000>;
0104 #address-cells = <3>;
0105 #size-cells = <2>;
0106 bus-range = <0x00 0xff>;
0107 device_type = "pci";
0108 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
0109 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
0110 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
0111 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
0112 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
0113 <0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
0114 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
0115 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
0116 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
0117 #interrupt-cells = <1>;
0118 interrupt-map-mask = <0 0 0 0>;
0119 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
0120 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
0121 clock-names = "pcie", "pcie_bus";
0122 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
0123 resets = <&cpg 319>;
0124 };
0125 };