0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm PCIe Endpoint Controller binding
0008
0009 maintainers:
0010 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0011
0012 allOf:
0013 - $ref: "pci-ep.yaml#"
0014
0015 properties:
0016 compatible:
0017 const: qcom,sdx55-pcie-ep
0018
0019 reg:
0020 items:
0021 - description: Qualcomm-specific PARF configuration registers
0022 - description: DesignWare PCIe registers
0023 - description: External local bus interface registers
0024 - description: Address Translation Unit (ATU) registers
0025 - description: Memory region used to map remote RC address space
0026 - description: BAR memory region
0027
0028 reg-names:
0029 items:
0030 - const: parf
0031 - const: dbi
0032 - const: elbi
0033 - const: atu
0034 - const: addr_space
0035 - const: mmio
0036
0037 clocks:
0038 items:
0039 - description: PCIe Auxiliary clock
0040 - description: PCIe CFG AHB clock
0041 - description: PCIe Master AXI clock
0042 - description: PCIe Slave AXI clock
0043 - description: PCIe Slave Q2A AXI clock
0044 - description: PCIe Sleep clock
0045 - description: PCIe Reference clock
0046
0047 clock-names:
0048 items:
0049 - const: aux
0050 - const: cfg
0051 - const: bus_master
0052 - const: bus_slave
0053 - const: slave_q2a
0054 - const: sleep
0055 - const: ref
0056
0057 qcom,perst-regs:
0058 description: Reference to a syscon representing TCSR followed by the two
0059 offsets within syscon for Perst enable and Perst separation
0060 enable registers
0061 $ref: "/schemas/types.yaml#/definitions/phandle-array"
0062 items:
0063 minItems: 3
0064 maxItems: 3
0065
0066 interrupts:
0067 items:
0068 - description: PCIe Global interrupt
0069 - description: PCIe Doorbell interrupt
0070
0071 interrupt-names:
0072 items:
0073 - const: global
0074 - const: doorbell
0075
0076 reset-gpios:
0077 description: GPIO used as PERST# input signal
0078 maxItems: 1
0079
0080 wake-gpios:
0081 description: GPIO used as WAKE# output signal
0082 maxItems: 1
0083
0084 resets:
0085 maxItems: 1
0086
0087 reset-names:
0088 const: core
0089
0090 power-domains:
0091 maxItems: 1
0092
0093 phys:
0094 maxItems: 1
0095
0096 phy-names:
0097 const: pciephy
0098
0099 num-lanes:
0100 default: 2
0101
0102 required:
0103 - compatible
0104 - reg
0105 - reg-names
0106 - clocks
0107 - clock-names
0108 - qcom,perst-regs
0109 - interrupts
0110 - interrupt-names
0111 - reset-gpios
0112 - resets
0113 - reset-names
0114 - power-domains
0115
0116 unevaluatedProperties: false
0117
0118 examples:
0119 - |
0120 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
0121 #include <dt-bindings/gpio/gpio.h>
0122 #include <dt-bindings/interrupt-controller/arm-gic.h>
0123 pcie_ep: pcie-ep@40000000 {
0124 compatible = "qcom,sdx55-pcie-ep";
0125 reg = <0x01c00000 0x3000>,
0126 <0x40000000 0xf1d>,
0127 <0x40000f20 0xc8>,
0128 <0x40001000 0x1000>,
0129 <0x40002000 0x1000>,
0130 <0x01c03000 0x3000>;
0131 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
0132 "mmio";
0133
0134 clocks = <&gcc GCC_PCIE_AUX_CLK>,
0135 <&gcc GCC_PCIE_CFG_AHB_CLK>,
0136 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
0137 <&gcc GCC_PCIE_SLV_AXI_CLK>,
0138 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
0139 <&gcc GCC_PCIE_SLEEP_CLK>,
0140 <&gcc GCC_PCIE_0_CLKREF_CLK>;
0141 clock-names = "aux", "cfg", "bus_master", "bus_slave",
0142 "slave_q2a", "sleep", "ref";
0143
0144 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
0145
0146 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
0147 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
0148 interrupt-names = "global", "doorbell";
0149 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
0150 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
0151 resets = <&gcc GCC_PCIE_BCR>;
0152 reset-names = "core";
0153 power-domains = <&gcc PCIE_GDSC>;
0154 phys = <&pcie0_lane>;
0155 phy-names = "pciephy";
0156 max-link-speed = <3>;
0157 num-lanes = <2>;
0158 };
