0001 PCI bus bridges have standardized Device Tree bindings:
0002
0003 PCI Bus Binding to: IEEE Std 1275-1994
0004 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
0005
0006 And for the interrupt mapping part:
0007
0008 Open Firmware Recommended Practice: Interrupt Mapping
0009 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
0010
0011 Additionally to the properties specified in the above standards a host bridge
0012 driver implementation may support the following properties:
0013
0014 - linux,pci-domain:
0015 If present this property assigns a fixed PCI domain number to a host bridge,
0016 otherwise an unstable (across boots) unique number will be assigned.
0017 It is required to either not set this property at all or set it for all
0018 host bridges in the system, otherwise potentially conflicting domain numbers
0019 may be assigned to root buses behind different host bridges. The domain
0020 number for each host bridge in the system must be unique.
0021 - max-link-speed:
0022 If present this property specifies PCI gen for link capability. Host
0023 drivers could add this as a strategy to avoid unnecessary operation for
0024 unsupported link speed, for instance, trying to do training for
0025 unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
0026 for gen2, and '1' for gen1. Any other values are invalid.
0027 - reset-gpios:
0028 If present this property specifies PERST# GPIO. Host drivers can parse the
0029 GPIO and apply fundamental reset to endpoints.
0030 - supports-clkreq:
0031 If present this property specifies that CLKREQ signal routing exists from
0032 root port to downstream device and host bridge drivers can do programming
0033 which depends on CLKREQ signal existence. For example, programming root port
0034 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
0035
0036 PCI-PCI Bridge properties
0037 -------------------------
0038
0039 PCIe root ports and switch ports may be described explicitly in the device
0040 tree, as children of the host bridge node. Even though those devices are
0041 discoverable by probing, it might be necessary to describe properties that
0042 aren't provided by standard PCIe capabilities.
0043
0044 Required properties:
0045
0046 - reg:
0047 Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
0048 document, it is a five-cell address encoded as (phys.hi phys.mid
0049 phys.lo size.hi size.lo). phys.hi should contain the device's BDF as
0050 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be zero.
0051
0052 The bus number is defined by firmware, through the standard bridge
0053 configuration mechanism. If this port is a switch port, then firmware
0054 allocates the bus number and writes it into the Secondary Bus Number
0055 register of the bridge directly above this port. Otherwise, the bus
0056 number of a root port is the first number in the bus-range property,
0057 defaulting to zero.
0058
0059 If firmware leaves the ARI Forwarding Enable bit set in the bridge
0060 above this port, then phys.hi contains the 8-bit function number as
0061 0b00000000 bbbbbbbb ffffffff 00000000. Note that the PCIe specification
0062 recommends that firmware only leaves ARI enabled when it knows that the
0063 OS is ARI-aware.
0064
0065 Optional properties:
0066
0067 - external-facing:
0068 When present, the port is external-facing. All bridges and endpoints
0069 downstream of this port are external to the machine. The OS can, for
0070 example, use this information to identify devices that cannot be
0071 trusted with relaxed DMA protection, as users could easily attach
0072 malicious devices to this port.
0073
0074 Example:
0075
0076 pcie@10000000 {
0077 compatible = "pci-host-ecam-generic";
0078 ...
0079 pcie@0008 {
0080 /* Root port 00:01.0 is external-facing */
0081 reg = <0x00000800 0 0 0 0>;
0082 external-facing;
0083 };
0084 };
