0001 * Marvell Armada 7K/8K PCIe interface
0002
0003 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
0004 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
0005
0006 Required properties:
0007 - compatible: "marvell,armada8k-pcie"
0008 - reg: must contain two register regions
0009 - the control register region
0010 - the config space region
0011 - reg-names:
0012 - "ctrl" for the control register region
0013 - "config" for the config space region
0014 - interrupts: Interrupt specifier for the PCIe controller
0015 - clocks: reference to the PCIe controller clocks
0016 - clock-names: mandatory if there is a second clock, in this case the
0017 name must be "core" for the first clock and "reg" for the second
0018 one
0019
0020 Optional properties:
0021 - phys: phandle(s) to PHY node(s) following the generic PHY bindings.
0022 Either 1, 2 or 4 PHYs might be needed depending on the number of
0023 PCIe lanes.
0024 - phy-names: names of the PHYs corresponding to the number of lanes.
0025 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
0026 2 PHYs.
0027
0028 Example:
0029
0030 pcie@f2600000 {
0031 compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
0032 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
0033 reg-names = "ctrl", "config";
0034 #address-cells = <3>;
0035 #size-cells = <2>;
0036 #interrupt-cells = <1>;
0037 device_type = "pci";
0038 dma-coherent;
0039
0040 bus-range = <0 0xff>;
0041 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
0042 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
0043 interrupt-map-mask = <0 0 0 0>;
0044 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0045 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
0046 num-lanes = <1>;
0047 clocks = <&cpm_syscon0 1 13>;
0048 };
