0001 NVIDIA Tegra PCIe controller
0002
0003 Required properties:
0004 - compatible: Must be:
0005 - "nvidia,tegra20-pcie": for Tegra20
0006 - "nvidia,tegra30-pcie": for Tegra30
0007 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
0008 - "nvidia,tegra210-pcie": for Tegra210
0009 - "nvidia,tegra186-pcie": for Tegra186
0010 - power-domains: To ungate power partition by BPMP powergate driver. Must
0011 contain BPMP phandle and PCIe power partition ID. This is required only
0012 for Tegra186.
0013 - device_type: Must be "pci"
0014 - reg: A list of physical base address and length for each set of controller
0015 registers. Must contain an entry for each entry in the reg-names property.
0016 - reg-names: Must include the following entries:
0017 "pads": PADS registers
0018 "afi": AFI registers
0019 "cs": configuration space region
0020 - interrupts: A list of interrupt outputs of the controller. Must contain an
0021 entry for each entry in the interrupt-names property.
0022 - interrupt-names: Must include the following entries:
0023 "intr": The Tegra interrupt that is asserted for controller interrupts
0024 "msi": The Tegra interrupt that is asserted when an MSI is received
0025 - bus-range: Range of bus numbers associated with this controller
0026 - #address-cells: Address representation for root ports (must be 3)
0027 - cell 0 specifies the bus and device numbers of the root port:
0028 [23:16]: bus number
0029 [15:11]: device number
0030 - cell 1 denotes the upper 32 address bits and should be 0
0031 - cell 2 contains the lower 32 address bits and is used to translate to the
0032 CPU address space
0033 - #size-cells: Size representation for root ports (must be 2)
0034 - ranges: Describes the translation of addresses for root ports and standard
0035 PCI regions. The entries must be 6 cells each, where the first three cells
0036 correspond to the address as described for the #address-cells property
0037 above, the fourth cell is the physical CPU address to translate to and the
0038 fifth and six cells are as described for the #size-cells property above.
0039 - The first two entries are expected to translate the addresses for the root
0040 port registers, which are referenced by the assigned-addresses property of
0041 the root port nodes (see below).
0042 - The remaining entries setup the mapping for the standard I/O, memory and
0043 prefetchable PCI regions. The first cell determines the type of region
0044 that is setup:
0045 - 0x81000000: I/O memory region
0046 - 0x82000000: non-prefetchable memory region
0047 - 0xc2000000: prefetchable memory region
0048 Please refer to the standard PCI bus binding document for a more detailed
0049 explanation.
0050 - #interrupt-cells: Size representation for interrupts (must be 1)
0051 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
0052 Please refer to the standard PCI bus binding document for a more detailed
0053 explanation.
0054 - clocks: Must contain an entry for each entry in clock-names.
0055 See ../clocks/clock-bindings.txt for details.
0056 - clock-names: Must include the following entries:
0057 - pex
0058 - afi
0059 - pll_e
0060 - cml (not required for Tegra20)
0061 - resets: Must contain an entry for each entry in reset-names.
0062 See ../reset/reset.txt for details.
0063 - reset-names: Must include the following entries:
0064 - pex
0065 - afi
0066 - pcie_x
0067
0068 Optional properties:
0069 - pinctrl-names: A list of pinctrl state names. Must contain the following
0070 entries:
0071 - "default": active state, puts PCIe I/O out of deep power down state
0072 - "idle": puts PCIe I/O into deep power down state
0073 - pinctrl-0: phandle for the default/active state of pin configurations.
0074 - pinctrl-1: phandle for the idle state of pin configurations.
0075
0076 Required properties on Tegra124 and later (deprecated):
0077 - phys: Must contain an entry for each entry in phy-names.
0078 - phy-names: Must include the following entries:
0079 - pcie
0080
0081 These properties are deprecated in favour of per-lane PHYs define in each of
0082 the root ports (see below).
0083
0084 Power supplies for Tegra20:
0085 - avdd-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
0086 - vdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
0087 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
0088 supply 1.05 V.
0089 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
0090 supply 1.05 V.
0091 - vddio-pex-clk-supply: Power supply for PCIe clock. Must supply 3.3 V.
0092
0093 Power supplies for Tegra30:
0094 - Required:
0095 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
0096 supply 1.05 V.
0097 - avdd-plle-supply: Power supply for PLLE, which is shared with SATA. Must
0098 supply 1.05 V.
0099 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
0100 supply 1.8 V.
0101 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
0102 Must supply 3.3 V.
0103 - Optional:
0104 - If lanes 0 to 3 are used:
0105 - avdd-pexa-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
0106 - vdd-pexa-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
0107 - If lanes 4 or 5 are used:
0108 - avdd-pexb-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
0109 - vdd-pexb-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
0110
0111 Power supplies for Tegra124:
0112 - Required:
0113 - avddio-pex-supply: Power supply for analog PCIe logic. Must supply 1.05 V.
0114 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
0115 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
0116 Must supply 3.3 V.
0117 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
0118 supply 2.8-3.3 V.
0119
0120 Power supplies for Tegra210:
0121 - Required:
0122 - hvddio-pex-supply: High-voltage supply for PCIe I/O and PCIe output
0123 clocks. Must supply 1.8 V.
0124 - dvddio-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
0125 - vddio-pex-ctl-supply: Power supply for PCIe control I/O partition. Must
0126 supply 1.8 V.
0127
0128 Power supplies for Tegra186:
0129 - Required:
0130 - dvdd-pex-supply: Power supply for digital PCIe I/O. Must supply 1.05 V.
0131 - hvdd-pex-pll-supply: High-voltage supply for PLLE (shared with USB3). Must
0132 supply 1.8 V.
0133 - hvdd-pex-supply: High-voltage supply for PCIe I/O and PCIe output clocks.
0134 Must supply 1.8 V.
0135 - vddio-pexctl-aud-supply: Power supply for PCIe side band signals. Must
0136 supply 1.8 V.
0137
0138 Root ports are defined as subnodes of the PCIe controller node.
0139
0140 Required properties:
0141 - device_type: Must be "pci"
0142 - assigned-addresses: Address and size of the port configuration registers
0143 - reg: PCI bus address of the root port
0144 - #address-cells: Must be 3
0145 - #size-cells: Must be 2
0146 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
0147 property is sufficient.
0148 - nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
0149 are:
0150 - Root port 0 uses 4 lanes, root port 1 is unused.
0151 - Both root ports use 2 lanes.
0152
0153 Required properties for Tegra124 and later:
0154 - phys: Must contain an phandle to a PHY for each entry in phy-names.
0155 - phy-names: Must include an entry for each active lane. Note that the number
0156 of entries does not have to (though usually will) be equal to the specified
0157 number of lanes in the nvidia,num-lanes property. Entries are of the form
0158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
0159
0160 Examples:
0161 =========
0162
0163 Tegra20:
0164 --------
0165
0166 SoC DTSI:
0167
0168 pcie-controller@80003000 {
0169 compatible = "nvidia,tegra20-pcie";
0170 device_type = "pci";
0171 reg = <0x80003000 0x00000800 /* PADS registers */
0172 0x80003800 0x00000200 /* AFI registers */
0173 0x90000000 0x10000000>; /* configuration space */
0174 reg-names = "pads", "afi", "cs";
0175 interrupts = <0 98 0x04 /* controller interrupt */
0176 0 99 0x04>; /* MSI interrupt */
0177 interrupt-names = "intr", "msi";
0178
0179 #interrupt-cells = <1>;
0180 interrupt-map-mask = <0 0 0 0>;
0181 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0182
0183 bus-range = <0x00 0xff>;
0184 #address-cells = <3>;
0185 #size-cells = <2>;
0186
0187 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
0188 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
0189 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
0190 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
0191 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
0192
0193 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 118>;
0194 clock-names = "pex", "afi", "pll_e";
0195 resets = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>;
0196 reset-names = "pex", "afi", "pcie_x";
0197 status = "disabled";
0198
0199 pci@1,0 {
0200 device_type = "pci";
0201 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
0202 reg = <0x000800 0 0 0 0>;
0203 status = "disabled";
0204
0205 #address-cells = <3>;
0206 #size-cells = <2>;
0207
0208 ranges;
0209
0210 nvidia,num-lanes = <2>;
0211 };
0212
0213 pci@2,0 {
0214 device_type = "pci";
0215 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
0216 reg = <0x001000 0 0 0 0>;
0217 status = "disabled";
0218
0219 #address-cells = <3>;
0220 #size-cells = <2>;
0221
0222 ranges;
0223
0224 nvidia,num-lanes = <2>;
0225 };
0226 };
0227
0228 Board DTS:
0229
0230 pcie-controller@80003000 {
0231 status = "okay";
0232
0233 vdd-supply = <&pci_vdd_reg>;
0234 pex-clk-supply = <&pci_clk_reg>;
0235
0236 /* root port 00:01.0 */
0237 pci@1,0 {
0238 status = "okay";
0239
0240 /* bridge 01:00.0 (optional) */
0241 pci@0,0 {
0242 reg = <0x010000 0 0 0 0>;
0243
0244 #address-cells = <3>;
0245 #size-cells = <2>;
0246
0247 device_type = "pci";
0248
0249 /* endpoint 02:00.0 */
0250 pci@0,0 {
0251 reg = <0x020000 0 0 0 0>;
0252 };
0253 };
0254 };
0255 };
0256
0257 Note that devices on the PCI bus are dynamically discovered using PCI's bus
0258 enumeration and therefore don't need corresponding device nodes in DT. However
0259 if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
0260 device nodes need to be added in order to allow the bus' children to be
0261 instantiated at the proper location in the operating system's device tree (as
0262 illustrated by the optional nodes in the example above).
0263
0264 Tegra30:
0265 --------
0266
0267 SoC DTSI:
0268
0269 pcie-controller@3000 {
0270 compatible = "nvidia,tegra30-pcie";
0271 device_type = "pci";
0272 reg = <0x00003000 0x00000800 /* PADS registers */
0273 0x00003800 0x00000200 /* AFI registers */
0274 0x10000000 0x10000000>; /* configuration space */
0275 reg-names = "pads", "afi", "cs";
0276 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
0277 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0278 interrupt-names = "intr", "msi";
0279
0280 #interrupt-cells = <1>;
0281 interrupt-map-mask = <0 0 0 0>;
0282 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0283
0284 bus-range = <0x00 0xff>;
0285 #address-cells = <3>;
0286 #size-cells = <2>;
0287
0288 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
0289 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
0290 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
0291 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
0292 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
0293 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
0294
0295 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
0296 <&tegra_car TEGRA30_CLK_AFI>,
0297 <&tegra_car TEGRA30_CLK_PLL_E>,
0298 <&tegra_car TEGRA30_CLK_CML0>;
0299 clock-names = "pex", "afi", "pll_e", "cml";
0300 resets = <&tegra_car 70>,
0301 <&tegra_car 72>,
0302 <&tegra_car 74>;
0303 reset-names = "pex", "afi", "pcie_x";
0304 status = "disabled";
0305
0306 pci@1,0 {
0307 device_type = "pci";
0308 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
0309 reg = <0x000800 0 0 0 0>;
0310 status = "disabled";
0311
0312 #address-cells = <3>;
0313 #size-cells = <2>;
0314 ranges;
0315
0316 nvidia,num-lanes = <2>;
0317 };
0318
0319 pci@2,0 {
0320 device_type = "pci";
0321 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
0322 reg = <0x001000 0 0 0 0>;
0323 status = "disabled";
0324
0325 #address-cells = <3>;
0326 #size-cells = <2>;
0327 ranges;
0328
0329 nvidia,num-lanes = <2>;
0330 };
0331
0332 pci@3,0 {
0333 device_type = "pci";
0334 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
0335 reg = <0x001800 0 0 0 0>;
0336 status = "disabled";
0337
0338 #address-cells = <3>;
0339 #size-cells = <2>;
0340 ranges;
0341
0342 nvidia,num-lanes = <2>;
0343 };
0344 };
0345
0346 Board DTS:
0347
0348 pcie-controller@3000 {
0349 status = "okay";
0350
0351 avdd-pexa-supply = <&ldo1_reg>;
0352 vdd-pexa-supply = <&ldo1_reg>;
0353 avdd-pexb-supply = <&ldo1_reg>;
0354 vdd-pexb-supply = <&ldo1_reg>;
0355 avdd-pex-pll-supply = <&ldo1_reg>;
0356 avdd-plle-supply = <&ldo1_reg>;
0357 vddio-pex-ctl-supply = <&sys_3v3_reg>;
0358 hvdd-pex-supply = <&sys_3v3_pexs_reg>;
0359
0360 pci@1,0 {
0361 status = "okay";
0362 };
0363
0364 pci@3,0 {
0365 status = "okay";
0366 };
0367 };
0368
0369 Tegra124:
0370 ---------
0371
0372 SoC DTSI:
0373
0374 pcie-controller@1003000 {
0375 compatible = "nvidia,tegra124-pcie";
0376 device_type = "pci";
0377 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
0378 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
0379 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
0380 reg-names = "pads", "afi", "cs";
0381 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0382 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0383 interrupt-names = "intr", "msi";
0384
0385 #interrupt-cells = <1>;
0386 interrupt-map-mask = <0 0 0 0>;
0387 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0388
0389 bus-range = <0x00 0xff>;
0390 #address-cells = <3>;
0391 #size-cells = <2>;
0392
0393 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
0394 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
0395 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
0396 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
0397 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
0398
0399 clocks = <&tegra_car TEGRA124_CLK_PCIE>,
0400 <&tegra_car TEGRA124_CLK_AFI>,
0401 <&tegra_car TEGRA124_CLK_PLL_E>,
0402 <&tegra_car TEGRA124_CLK_CML0>;
0403 clock-names = "pex", "afi", "pll_e", "cml";
0404 resets = <&tegra_car 70>,
0405 <&tegra_car 72>,
0406 <&tegra_car 74>;
0407 reset-names = "pex", "afi", "pcie_x";
0408 status = "disabled";
0409
0410 pci@1,0 {
0411 device_type = "pci";
0412 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
0413 reg = <0x000800 0 0 0 0>;
0414 status = "disabled";
0415
0416 #address-cells = <3>;
0417 #size-cells = <2>;
0418 ranges;
0419
0420 nvidia,num-lanes = <2>;
0421 };
0422
0423 pci@2,0 {
0424 device_type = "pci";
0425 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
0426 reg = <0x001000 0 0 0 0>;
0427 status = "disabled";
0428
0429 #address-cells = <3>;
0430 #size-cells = <2>;
0431 ranges;
0432
0433 nvidia,num-lanes = <1>;
0434 };
0435 };
0436
0437 Board DTS:
0438
0439 pcie-controller@1003000 {
0440 status = "okay";
0441
0442 avddio-pex-supply = <&vdd_1v05_run>;
0443 dvddio-pex-supply = <&vdd_1v05_run>;
0444 avdd-pex-pll-supply = <&vdd_1v05_run>;
0445 hvdd-pex-supply = <&vdd_3v3_lp0>;
0446 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
0447 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
0448 avdd-pll-erefe-supply = <&avdd_1v05_run>;
0449
0450 /* Mini PCIe */
0451 pci@1,0 {
0452 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
0453 phy-names = "pcie-0";
0454 status = "okay";
0455 };
0456
0457 /* Gigabit Ethernet */
0458 pci@2,0 {
0459 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
0460 phy-names = "pcie-0";
0461 status = "okay";
0462 };
0463 };
0464
0465 Tegra210:
0466 ---------
0467
0468 SoC DTSI:
0469
0470 pcie-controller@1003000 {
0471 compatible = "nvidia,tegra210-pcie";
0472 device_type = "pci";
0473 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
0474 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
0475 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
0476 reg-names = "pads", "afi", "cs";
0477 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0478 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0479 interrupt-names = "intr", "msi";
0480
0481 #interrupt-cells = <1>;
0482 interrupt-map-mask = <0 0 0 0>;
0483 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
0484
0485 bus-range = <0x00 0xff>;
0486 #address-cells = <3>;
0487 #size-cells = <2>;
0488
0489 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
0490 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
0491 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
0492 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
0493 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
0494
0495 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
0496 <&tegra_car TEGRA210_CLK_AFI>,
0497 <&tegra_car TEGRA210_CLK_PLL_E>,
0498 <&tegra_car TEGRA210_CLK_CML0>;
0499 clock-names = "pex", "afi", "pll_e", "cml";
0500 resets = <&tegra_car 70>,
0501 <&tegra_car 72>,
0502 <&tegra_car 74>;
0503 reset-names = "pex", "afi", "pcie_x";
0504 status = "disabled";
0505
0506 pci@1,0 {
0507 device_type = "pci";
0508 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
0509 reg = <0x000800 0 0 0 0>;
0510 status = "disabled";
0511
0512 #address-cells = <3>;
0513 #size-cells = <2>;
0514 ranges;
0515
0516 nvidia,num-lanes = <4>;
0517 };
0518
0519 pci@2,0 {
0520 device_type = "pci";
0521 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
0522 reg = <0x001000 0 0 0 0>;
0523 status = "disabled";
0524
0525 #address-cells = <3>;
0526 #size-cells = <2>;
0527 ranges;
0528
0529 nvidia,num-lanes = <1>;
0530 };
0531 };
0532
0533 Board DTS:
0534
0535 pcie-controller@1003000 {
0536 status = "okay";
0537
0538 avdd-pll-uerefe-supply = <&avdd_1v05_pll>;
0539 hvddio-pex-supply = <&vdd_1v8>;
0540 dvddio-pex-supply = <&vdd_pex_1v05>;
0541 dvdd-pex-pll-supply = <&vdd_pex_1v05>;
0542 hvdd-pex-pll-e-supply = <&vdd_1v8>;
0543 vddio-pex-ctl-supply = <&vdd_1v8>;
0544
0545 pci@1,0 {
0546 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>,
0547 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
0548 <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>,
0549 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
0550 phy-names = "pcie-0", "pcie-1", "pcie-2", "pcie-3";
0551 status = "okay";
0552 };
0553
0554 pci@2,0 {
0555 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
0556 phy-names = "pcie-0";
0557 status = "okay";
0558 };
0559 };
0560
0561 Tegra186:
0562 ---------
0563
0564 SoC DTSI:
0565
0566 pcie@10003000 {
0567 compatible = "nvidia,tegra186-pcie";
0568 power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>;
0569 device_type = "pci";
0570 reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
0571 0x0 0x10003800 0x0 0x00000800 /* AFI registers */
0572 0x0 0x40000000 0x0 0x10000000>; /* configuration space */
0573 reg-names = "pads", "afi", "cs";
0574
0575 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0576 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0577 interrupt-names = "intr", "msi";
0578
0579 #interrupt-cells = <1>;
0580 interrupt-map-mask = <0 0 0 0>;
0581 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0582
0583 bus-range = <0x00 0xff>;
0584 #address-cells = <3>;
0585 #size-cells = <2>;
0586
0587 ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */
0588 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */
0589 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */
0590 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */
0591 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */
0592 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */
0593
0594 clocks = <&bpmp TEGRA186_CLK_AFI>,
0595 <&bpmp TEGRA186_CLK_PCIE>,
0596 <&bpmp TEGRA186_CLK_PLLE>;
0597 clock-names = "afi", "pex", "pll_e";
0598
0599 resets = <&bpmp TEGRA186_RESET_AFI>,
0600 <&bpmp TEGRA186_RESET_PCIE>,
0601 <&bpmp TEGRA186_RESET_PCIEXCLK>;
0602 reset-names = "afi", "pex", "pcie_x";
0603
0604 status = "disabled";
0605
0606 pci@1,0 {
0607 device_type = "pci";
0608 assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>;
0609 reg = <0x000800 0 0 0 0>;
0610 status = "disabled";
0611
0612 #address-cells = <3>;
0613 #size-cells = <2>;
0614 ranges;
0615
0616 nvidia,num-lanes = <2>;
0617 };
0618
0619 pci@2,0 {
0620 device_type = "pci";
0621 assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>;
0622 reg = <0x001000 0 0 0 0>;
0623 status = "disabled";
0624
0625 #address-cells = <3>;
0626 #size-cells = <2>;
0627 ranges;
0628
0629 nvidia,num-lanes = <1>;
0630 };
0631
0632 pci@3,0 {
0633 device_type = "pci";
0634 assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>;
0635 reg = <0x001800 0 0 0 0>;
0636 status = "disabled";
0637
0638 #address-cells = <3>;
0639 #size-cells = <2>;
0640 ranges;
0641
0642 nvidia,num-lanes = <1>;
0643 };
0644 };
0645
0646 Board DTS:
0647
0648 pcie@10003000 {
0649 status = "okay";
0650
0651 dvdd-pex-supply = <&vdd_pex>;
0652 hvdd-pex-pll-supply = <&vdd_1v8>;
0653 hvdd-pex-supply = <&vdd_1v8>;
0654 vddio-pexctl-aud-supply = <&vdd_1v8>;
0655
0656 pci@1,0 {
0657 nvidia,num-lanes = <4>;
0658 status = "okay";
0659 };
0660
0661 pci@2,0 {
0662 nvidia,num-lanes = <0>;
0663 status = "disabled";
0664 };
0665
0666 pci@3,0 {
0667 nvidia,num-lanes = <1>;
0668 status = "disabled";
0669 };
0670 };
