0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012 - Vidya Sagar <vidyas@nvidia.com>
0013
0014 description: |
0015 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
0016 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
0017 the controller instances are dual mode where in they can work either in
0018 Root Port mode or Endpoint mode but one at a time.
0019
0020 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
0021 tree bindings.
0022
0023 properties:
0024 compatible:
0025 enum:
0026 - nvidia,tegra194-pcie
0027 - nvidia,tegra234-pcie
0028
0029 reg:
0030 items:
0031 - description: controller's application logic registers
0032 - description: configuration registers
0033 - description: iATU and DMA registers. This is where the iATU (internal
0034 Address Translation Unit) registers of the PCIe core are made
0035 available for software access.
0036 - description: aperture where the Root Port's own configuration
0037 registers are available.
0038
0039 reg-names:
0040 items:
0041 - const: appl
0042 - const: config
0043 - const: atu_dma
0044 - const: dbi
0045
0046 interrupts:
0047 items:
0048 - description: controller interrupt
0049 - description: MSI interrupt
0050
0051 interrupt-names:
0052 items:
0053 - const: intr
0054 - const: msi
0055
0056 clocks:
0057 items:
0058 - description: module clock
0059
0060 clock-names:
0061 items:
0062 - const: core
0063
0064 resets:
0065 items:
0066 - description: APB bus interface reset
0067 - description: module reset
0068
0069 reset-names:
0070 items:
0071 - const: apb
0072 - const: core
0073
0074 phys:
0075 minItems: 1
0076 maxItems: 8
0077
0078 phy-names:
0079 minItems: 1
0080 items:
0081 - const: p2u-0
0082 - const: p2u-1
0083 - const: p2u-2
0084 - const: p2u-3
0085 - const: p2u-4
0086 - const: p2u-5
0087 - const: p2u-6
0088 - const: p2u-7
0089
0090 power-domains:
0091 maxItems: 1
0092 description: |
0093 A phandle to the node that controls power to the respective PCIe
0094 controller and a specifier name for the PCIe controller.
0095
0096 Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h"
0097 Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h"
0098
0099 interconnects:
0100 items:
0101 - description: memory read client
0102 - description: memory write client
0103
0104 interconnect-names:
0105 items:
0106 - const: dma-mem # read
0107 - const: write
0108
0109 dma-coherent: true
0110
0111 nvidia,bpmp:
0112 $ref: /schemas/types.yaml#/definitions/phandle-array
0113 description: |
0114 Must contain a pair of phandles to BPMP controller node followed by
0115 controller ID. Following are the controller IDs for each controller:
0116
0117 Tegra194
0118
0119 0: C0
0120 1: C1
0121 2: C2
0122 3: C3
0123 4: C4
0124 5: C5
0125
0126 Tegra234
0127
0128 0 : C0
0129 1 : C1
0130 2 : C2
0131 3 : C3
0132 4 : C4
0133 5 : C5
0134 6 : C6
0135 7 : C7
0136 8 : C8
0137 9 : C9
0138 10: C10
0139
0140 items:
0141 - items:
0142 - description: phandle to BPMP controller node
0143 - description: PCIe controller ID
0144 maximum: 10
0145
0146 nvidia,update-fc-fixup:
0147 description: |
0148 This is a boolean property and needs to be present to improve performance
0149 when a platform is designed in such a way that it satisfies at least one
0150 of the following conditions thereby enabling Root Port to exchange
0151 optimum number of FC (Flow Control) credits with downstream devices:
0152
0153 NOTE: This is applicable only for Tegra194.
0154
0155 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
0156 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
0157 a) speed is Gen-2 and MPS is 256B
0158 b) speed is >= Gen-3 with any MPS
0159
0160 $ref: /schemas/types.yaml#/definitions/flag
0161
0162 nvidia,aspm-cmrt-us:
0163 description: Common Mode Restore Time for proper operation of ASPM to be
0164 specified in microseconds
0165
0166 nvidia,aspm-pwr-on-t-us:
0167 description: Power On time for proper operation of ASPM to be specified in
0168 microseconds
0169
0170 nvidia,aspm-l0s-entrance-latency-us:
0171 description: ASPM L0s entrance latency to be specified in microseconds
0172
0173 vddio-pex-ctl-supply:
0174 description: A phandle to the regulator supply for PCIe side band signals.
0175
0176 vpcie3v3-supply:
0177 description: A phandle to the regulator node that supplies 3.3V to the slot
0178 if the platform has one such slot, e.g., x16 slot owned by C5 controller
0179 in p2972-0000 platform.
0180
0181 vpcie12v-supply:
0182 description: A phandle to the regulator node that supplies 12V to the slot
0183 if the platform has one such slot, e.g., x16 slot owned by C5 controller
0184 in p2972-0000 platform.
0185
0186 nvidia,enable-srns:
0187 description: |
0188 This boolean property needs to be present if the controller is
0189 configured to operate in SRNS (Separate Reference Clocks with No
0190 Spread-Spectrum Clocking). NOTE: This is applicable only for
0191 Tegra234.
0192
0193 $ref: /schemas/types.yaml#/definitions/flag
0194
0195 nvidia,enable-ext-refclk:
0196 description: |
0197 This boolean property needs to be present if the controller is
0198 configured to use the reference clocking coming in from an external
0199 clock source instead of using the internal clock source.
0200
0201 $ref: /schemas/types.yaml#/definitions/flag
0202
0203 allOf:
0204 - $ref: /schemas/pci/snps,dw-pcie.yaml#
0205
0206 unevaluatedProperties: false
0207
0208 required:
0209 - interrupts
0210 - interrupt-names
0211 - interrupt-map
0212 - interrupt-map-mask
0213 - clocks
0214 - clock-names
0215 - resets
0216 - reset-names
0217 - power-domains
0218 - vddio-pex-ctl-supply
0219 - num-lanes
0220 - phys
0221 - phy-names
0222 - nvidia,bpmp
0223
0224 examples:
0225 - |
0226 #include <dt-bindings/clock/tegra194-clock.h>
0227 #include <dt-bindings/interrupt-controller/arm-gic.h>
0228 #include <dt-bindings/power/tegra194-powergate.h>
0229 #include <dt-bindings/reset/tegra194-reset.h>
0230
0231 bus@0 {
0232 #address-cells = <2>;
0233 #size-cells = <2>;
0234 ranges = <0x0 0x0 0x0 0x8 0x0>;
0235
0236 pcie@14180000 {
0237 compatible = "nvidia,tegra194-pcie";
0238 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
0239 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
0240 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
0241 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
0242 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
0243 reg-names = "appl", "config", "atu_dma", "dbi";
0244
0245 #address-cells = <3>;
0246 #size-cells = <2>;
0247 device_type = "pci";
0248 num-lanes = <8>;
0249 linux,pci-domain = <0>;
0250
0251 pinctrl-names = "default";
0252 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
0253
0254 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
0255 clock-names = "core";
0256
0257 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
0258 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
0259 reset-names = "apb", "core";
0260
0261 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0262 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0263 interrupt-names = "intr", "msi";
0264
0265 #interrupt-cells = <1>;
0266 interrupt-map-mask = <0 0 0 0>;
0267 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
0268
0269 nvidia,bpmp = <&bpmp 0>;
0270
0271 supports-clkreq;
0272 nvidia,aspm-cmrt-us = <60>;
0273 nvidia,aspm-pwr-on-t-us = <20>;
0274 nvidia,aspm-l0s-entrance-latency-us = <3>;
0275
0276 bus-range = <0x0 0xff>;
0277 ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, /* downstream I/O */
0278 <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
0279 <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
0280
0281 vddio-pex-ctl-supply = <&vdd_1v8ao>;
0282 vpcie3v3-supply = <&vdd_3v3_pcie>;
0283 vpcie12v-supply = <&vdd_12v_pcie>;
0284
0285 phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
0286 <&p2u_hsio_5>;
0287 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
0288 };
0289 };
0290
0291 - |
0292 #include <dt-bindings/clock/tegra234-clock.h>
0293 #include <dt-bindings/interrupt-controller/arm-gic.h>
0294 #include <dt-bindings/power/tegra234-powergate.h>
0295 #include <dt-bindings/reset/tegra234-reset.h>
0296
0297 bus@0 {
0298 #address-cells = <2>;
0299 #size-cells = <2>;
0300 ranges = <0x0 0x0 0x0 0x8 0x0>;
0301
0302 pcie@14160000 {
0303 compatible = "nvidia,tegra234-pcie";
0304 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
0305 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
0306 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
0307 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
0308 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
0309 reg-names = "appl", "config", "atu_dma", "dbi";
0310
0311 #address-cells = <3>;
0312 #size-cells = <2>;
0313 device_type = "pci";
0314 num-lanes = <4>;
0315 num-viewport = <8>;
0316 linux,pci-domain = <4>;
0317
0318 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
0319 clock-names = "core";
0320
0321 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
0322 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
0323 reset-names = "apb", "core";
0324
0325 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
0326 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
0327 interrupt-names = "intr", "msi";
0328
0329 #interrupt-cells = <1>;
0330 interrupt-map-mask = <0 0 0 0>;
0331 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
0332
0333 nvidia,bpmp = <&bpmp 4>;
0334
0335 nvidia,aspm-cmrt-us = <60>;
0336 nvidia,aspm-pwr-on-t-us = <20>;
0337 nvidia,aspm-l0s-entrance-latency-us = <3>;
0338
0339 bus-range = <0x0 0xff>;
0340 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */
0341 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
0342 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */
0343
0344 vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
0345
0346 phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
0347 <&p2u_hsio_7>;
0348 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
0349 };
0350 };
