0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
0008
0009 maintainers:
0010 - Thierry Reding <thierry.reding@gmail.com>
0011 - Jon Hunter <jonathanh@nvidia.com>
0012 - Vidya Sagar <vidyas@nvidia.com>
0013
0014 description: |
0015 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
0016 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
0017 of the controller instances are dual mode; they can work either in Root
0018 Port mode or Endpoint mode but one at a time.
0019
0020 On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
0021 On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode.
0022
0023 Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
0024 operate in the Endpoint mode because of the way the platform is designed.
0025
0026 properties:
0027 compatible:
0028 enum:
0029 - nvidia,tegra194-pcie-ep
0030 - nvidia,tegra234-pcie-ep
0031
0032 reg:
0033 items:
0034 - description: controller's application logic registers
0035 - description: iATU and DMA registers. This is where the iATU (internal
0036 Address Translation Unit) registers of the PCIe core are made
0037 available for software access.
0038 - description: aperture where the Root Port's own configuration
0039 registers are available.
0040 - description: aperture used to map the remote Root Complex address space
0041
0042 reg-names:
0043 items:
0044 - const: appl
0045 - const: atu_dma
0046 - const: dbi
0047 - const: addr_space
0048
0049 interrupts:
0050 items:
0051 - description: controller interrupt
0052
0053 interrupt-names:
0054 items:
0055 - const: intr
0056
0057 clocks:
0058 items:
0059 - description: module clock
0060
0061 clock-names:
0062 items:
0063 - const: core
0064
0065 resets:
0066 items:
0067 - description: APB bus interface reset
0068 - description: module reset
0069
0070 reset-names:
0071 items:
0072 - const: apb
0073 - const: core
0074
0075 reset-gpios:
0076 description: Must contain a phandle to a GPIO controller followed by GPIO
0077 that is being used as PERST input signal. Please refer to pci.txt.
0078
0079 phys:
0080 minItems: 1
0081 maxItems: 8
0082
0083 phy-names:
0084 minItems: 1
0085 items:
0086 - const: p2u-0
0087 - const: p2u-1
0088 - const: p2u-2
0089 - const: p2u-3
0090 - const: p2u-4
0091 - const: p2u-5
0092 - const: p2u-6
0093 - const: p2u-7
0094
0095 power-domains:
0096 maxItems: 1
0097 description: |
0098 A phandle to the node that controls power to the respective PCIe
0099 controller and a specifier name for the PCIe controller.
0100
0101 Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h"
0102 Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h"
0103
0104 interconnects:
0105 items:
0106 - description: memory read client
0107 - description: memory write client
0108
0109 interconnect-names:
0110 items:
0111 - const: dma-mem # read
0112 - const: write
0113
0114 dma-coherent: true
0115
0116 nvidia,bpmp:
0117 $ref: /schemas/types.yaml#/definitions/phandle-array
0118 description: |
0119 Must contain a pair of phandles to BPMP controller node followed by
0120 controller ID. Following are the controller IDs for each controller:
0121
0122 Tegra194
0123
0124 0: C0
0125 1: C1
0126 2: C2
0127 3: C3
0128 4: C4
0129 5: C5
0130
0131 Tegra234
0132
0133 0 : C0
0134 1 : C1
0135 2 : C2
0136 3 : C3
0137 4 : C4
0138 5 : C5
0139 6 : C6
0140 7 : C7
0141 8 : C8
0142 9 : C9
0143 10: C10
0144
0145 items:
0146 - items:
0147 - description: phandle to BPMP controller node
0148 - description: PCIe controller ID
0149 maximum: 10
0150
0151 nvidia,aspm-cmrt-us:
0152 description: Common Mode Restore Time for proper operation of ASPM to be
0153 specified in microseconds
0154
0155 nvidia,aspm-pwr-on-t-us:
0156 description: Power On time for proper operation of ASPM to be specified in
0157 microseconds
0158
0159 nvidia,aspm-l0s-entrance-latency-us:
0160 description: ASPM L0s entrance latency to be specified in microseconds
0161
0162 vddio-pex-ctl-supply:
0163 description: A phandle to the regulator supply for PCIe side band signals
0164
0165 nvidia,refclk-select-gpios:
0166 maxItems: 1
0167 description: GPIO used to enable REFCLK to controller from the host
0168
0169 nvidia,enable-ext-refclk:
0170 description: |
0171 This boolean property needs to be present if the controller is configured
0172 to receive Reference Clock from the host.
0173 NOTE: This is applicable only for Tegra234.
0174
0175 $ref: /schemas/types.yaml#/definitions/flag
0176
0177 nvidia,enable-srns:
0178 description: |
0179 This boolean property needs to be present if the controller is
0180 configured to operate in SRNS (Separate Reference Clocks with No
0181 Spread-Spectrum Clocking). NOTE: This is applicable only for
0182 Tegra234.
0183
0184 $ref: /schemas/types.yaml#/definitions/flag
0185
0186 allOf:
0187 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
0188
0189 unevaluatedProperties: false
0190
0191 required:
0192 - interrupts
0193 - interrupt-names
0194 - clocks
0195 - clock-names
0196 - resets
0197 - reset-names
0198 - power-domains
0199 - reset-gpios
0200 - vddio-pex-ctl-supply
0201 - num-lanes
0202 - phys
0203 - phy-names
0204 - nvidia,bpmp
0205
0206 examples:
0207 - |
0208 #include <dt-bindings/clock/tegra194-clock.h>
0209 #include <dt-bindings/gpio/tegra194-gpio.h>
0210 #include <dt-bindings/interrupt-controller/arm-gic.h>
0211 #include <dt-bindings/power/tegra194-powergate.h>
0212 #include <dt-bindings/reset/tegra194-reset.h>
0213
0214 bus@0 {
0215 #address-cells = <2>;
0216 #size-cells = <2>;
0217 ranges = <0x0 0x0 0x0 0x8 0x0>;
0218
0219 pcie-ep@141a0000 {
0220 compatible = "nvidia,tegra194-pcie-ep";
0221 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
0222 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
0223 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
0224 <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
0225 reg-names = "appl", "atu_dma", "dbi", "addr_space";
0226 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
0227 interrupt-names = "intr";
0228
0229 clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
0230 clock-names = "core";
0231
0232 resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
0233 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
0234 reset-names = "apb", "core";
0235
0236 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
0237 pinctrl-names = "default";
0238 pinctrl-0 = <&clkreq_c5_bi_dir_state>;
0239
0240 nvidia,bpmp = <&bpmp 5>;
0241
0242 nvidia,aspm-cmrt-us = <60>;
0243 nvidia,aspm-pwr-on-t-us = <20>;
0244 nvidia,aspm-l0s-entrance-latency-us = <3>;
0245
0246 vddio-pex-ctl-supply = <&vdd_1v8ao>;
0247
0248 reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
0249
0250 nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
0251 GPIO_ACTIVE_HIGH>;
0252
0253 num-lanes = <8>;
0254
0255 phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
0256 <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
0257 <&p2u_nvhs_6>, <&p2u_nvhs_7>;
0258
0259 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
0260 "p2u-5", "p2u-6", "p2u-7";
0261 };
0262 };
0263
0264 - |
0265 #include <dt-bindings/clock/tegra234-clock.h>
0266 #include <dt-bindings/gpio/tegra234-gpio.h>
0267 #include <dt-bindings/interrupt-controller/arm-gic.h>
0268 #include <dt-bindings/power/tegra234-powergate.h>
0269 #include <dt-bindings/reset/tegra234-reset.h>
0270
0271 bus@0 {
0272 #address-cells = <2>;
0273 #size-cells = <2>;
0274 ranges = <0x0 0x0 0x0 0x8 0x0>;
0275
0276 pcie-ep@141a0000 {
0277 compatible = "nvidia,tegra234-pcie-ep";
0278 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
0279 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
0280 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
0281 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
0282 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
0283 reg-names = "appl", "atu_dma", "dbi", "addr_space";
0284
0285 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
0286 interrupt-names = "intr";
0287
0288 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
0289 clock-names = "core";
0290
0291 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
0292 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
0293 reset-names = "apb", "core";
0294
0295 nvidia,bpmp = <&bpmp 5>;
0296
0297 nvidia,enable-ext-refclk;
0298 nvidia,aspm-cmrt-us = <60>;
0299 nvidia,aspm-pwr-on-t-us = <20>;
0300 nvidia,aspm-l0s-entrance-latency-us = <3>;
0301
0302 vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
0303
0304 reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
0305
0306 nvidia,refclk-select-gpios = <&gpio_aon
0307 TEGRA234_AON_GPIO(AA, 4)
0308 GPIO_ACTIVE_HIGH>;
0309
0310 num-lanes = <8>;
0311
0312 phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
0313 <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
0314 <&p2u_nvhs_6>, <&p2u_nvhs_7>;
0315
0316 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
0317 "p2u-5", "p2u-6", "p2u-7";
0318 };
0319 };
