0001 * Marvell EBU PCIe interfaces
0002
0003 Mandatory properties:
0004
0005 - compatible: one of the following values:
0006 marvell,armada-370-pcie
0007 marvell,armada-xp-pcie
0008 marvell,dove-pcie
0009 marvell,kirkwood-pcie
0010 - #address-cells, set to <3>
0011 - #size-cells, set to <2>
0012 - #interrupt-cells, set to <1>
0013 - bus-range: PCI bus numbers covered
0014 - device_type, set to "pci"
0015 - ranges: ranges describing the MMIO registers to control the PCIe
0016 interfaces, and ranges describing the MBus windows needed to access
0017 the memory and I/O regions of each PCIe interface.
0018 - msi-parent: Link to the hardware entity that serves as the Message
0019 Signaled Interrupt controller for this PCI controller.
0020
0021 The ranges describing the MMIO registers have the following layout:
0022
0023 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
0024
0025 where:
0026
0027 * r is a 32-bits value that gives the offset of the MMIO
0028 registers of this PCIe interface, from the base of the internal
0029 registers.
0030
0031 * s is a 32-bits value that give the size of this MMIO
0032 registers area. This range entry translates the '0x82000000 0 r' PCI
0033 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
0034 of the internal register window (as identified by MBUS_ID(0xf0,
0035 0x01)).
0036
0037 The ranges describing the MBus windows have the following layout:
0038
0039 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
0040
0041 where:
0042
0043 * t is the type of the MBus window (as defined by the standard PCI DT
0044 bindings), 1 for I/O and 2 for memory.
0045
0046 * s is the PCI slot that corresponds to this PCIe interface
0047
0048 * w is the 'target ID' value for the MBus window
0049
0050 * a the 'attribute' value for the MBus window.
0051
0052 Since the location and size of the different MBus windows is not fixed in
0053 hardware, and only determined in runtime, those ranges cover the full first
0054 4 GB of the physical address space, and do not translate into a valid CPU
0055 address.
0056
0057 In addition, the device tree node must have sub-nodes describing each
0058 PCIe interface, having the following mandatory properties:
0059
0060 - reg: used only for interrupt mapping, so only the first four bytes
0061 are used to refer to the correct bus number and device number.
0062 - assigned-addresses: reference to the MMIO registers used to control
0063 this PCIe interface.
0064 - clocks: the clock associated to this PCIe interface
0065 - marvell,pcie-port: the physical PCIe port number
0066 - status: either "disabled" or "okay"
0067 - device_type, set to "pci"
0068 - #address-cells, set to <3>
0069 - #size-cells, set to <2>
0070 - #interrupt-cells, set to <1>
0071 - ranges, translating the MBus windows ranges of the parent node into
0072 standard PCI addresses.
0073 - interrupt-map-mask and interrupt-map, standard PCI properties to
0074 define the mapping of the PCIe interface to interrupt numbers.
0075
0076 and the following optional properties:
0077 - marvell,pcie-lane: the physical PCIe lane number, for ports having
0078 multiple lanes. If this property is not found, we assume that the
0079 value is 0.
0080 - num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
0081 - reset-gpios: optional GPIO to PERST#
0082 - reset-delay-us: delay in us to wait after reset de-assertion, if not
0083 specified will default to 100ms, as required by the PCIe specification.
0084 - interrupt-names: list of interrupt names, supported are:
0085 - "intx" - interrupt line triggered by one of the legacy interrupt
0086 - interrupts or interrupts-extended: List of the interrupt sources which
0087 corresponding to the "interrupt-names". If non-empty then also additional
0088 'interrupt-controller' subnode must be defined.
0089
0090 Example:
0091
0092 pcie-controller {
0093 compatible = "marvell,armada-xp-pcie";
0094 device_type = "pci";
0095
0096 #address-cells = <3>;
0097 #size-cells = <2>;
0098
0099 bus-range = <0x00 0xff>;
0100 msi-parent = <&mpic>;
0101
0102 ranges =
0103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
0104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
0105 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
0106 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
0107 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
0108 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
0109 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
0110 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
0111 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
0112 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
0113 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
0114 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
0115 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
0116 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
0117 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
0118 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
0119 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
0120 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
0121
0122 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
0123 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
0124 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
0125 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
0126 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
0127 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
0128 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
0129 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
0130
0131 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
0132 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
0133
0134 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
0135 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
0136
0137 pcie@1,0 {
0138 device_type = "pci";
0139 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
0140 reg = <0x0800 0 0 0 0>;
0141 #address-cells = <3>;
0142 #size-cells = <2>;
0143 #interrupt-cells = <1>;
0144 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0145 0x81000000 0 0 0x81000000 0x1 0 1 0>;
0146 interrupt-map-mask = <0 0 0 0>;
0147 interrupt-map = <0 0 0 0 &mpic 58>;
0148 marvell,pcie-port = <0>;
0149 marvell,pcie-lane = <0>;
0150 num-lanes = <1>;
0151 /* low-active PERST# reset on GPIO 25 */
0152 reset-gpios = <&gpio0 25 1>;
0153 /* wait 20ms for device settle after reset deassertion */
0154 reset-delay-us = <20000>;
0155 clocks = <&gateclk 5>;
0156 };
0157
0158 pcie@2,0 {
0159 device_type = "pci";
0160 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
0161 reg = <0x1000 0 0 0 0>;
0162 #address-cells = <3>;
0163 #size-cells = <2>;
0164 #interrupt-cells = <1>;
0165 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0166 0x81000000 0 0 0x81000000 0x2 0 1 0>;
0167 interrupt-map-mask = <0 0 0 0>;
0168 interrupt-map = <0 0 0 0 &mpic 59>;
0169 marvell,pcie-port = <0>;
0170 marvell,pcie-lane = <1>;
0171 num-lanes = <1>;
0172 clocks = <&gateclk 6>;
0173 };
0174
0175 pcie@3,0 {
0176 device_type = "pci";
0177 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
0178 reg = <0x1800 0 0 0 0>;
0179 #address-cells = <3>;
0180 #size-cells = <2>;
0181 #interrupt-cells = <1>;
0182 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0183 0x81000000 0 0 0x81000000 0x3 0 1 0>;
0184 interrupt-map-mask = <0 0 0 0>;
0185 interrupt-map = <0 0 0 0 &mpic 60>;
0186 marvell,pcie-port = <0>;
0187 marvell,pcie-lane = <2>;
0188 num-lanes = <1>;
0189 clocks = <&gateclk 7>;
0190 };
0191
0192 pcie@4,0 {
0193 device_type = "pci";
0194 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
0195 reg = <0x2000 0 0 0 0>;
0196 #address-cells = <3>;
0197 #size-cells = <2>;
0198 #interrupt-cells = <1>;
0199 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0200 0x81000000 0 0 0x81000000 0x4 0 1 0>;
0201 interrupt-map-mask = <0 0 0 0>;
0202 interrupt-map = <0 0 0 0 &mpic 61>;
0203 marvell,pcie-port = <0>;
0204 marvell,pcie-lane = <3>;
0205 num-lanes = <1>;
0206 clocks = <&gateclk 8>;
0207 };
0208
0209 pcie@5,0 {
0210 device_type = "pci";
0211 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
0212 reg = <0x2800 0 0 0 0>;
0213 #address-cells = <3>;
0214 #size-cells = <2>;
0215 #interrupt-cells = <1>;
0216 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0217 0x81000000 0 0 0x81000000 0x5 0 1 0>;
0218 interrupt-map-mask = <0 0 0 0>;
0219 interrupt-map = <0 0 0 0 &mpic 62>;
0220 marvell,pcie-port = <1>;
0221 marvell,pcie-lane = <0>;
0222 num-lanes = <1>;
0223 clocks = <&gateclk 9>;
0224 };
0225
0226 pcie@6,0 {
0227 device_type = "pci";
0228 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
0229 reg = <0x3000 0 0 0 0>;
0230 #address-cells = <3>;
0231 #size-cells = <2>;
0232 #interrupt-cells = <1>;
0233 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0234 0x81000000 0 0 0x81000000 0x6 0 1 0>;
0235 interrupt-map-mask = <0 0 0 0>;
0236 interrupt-map = <0 0 0 0 &mpic 63>;
0237 marvell,pcie-port = <1>;
0238 marvell,pcie-lane = <1>;
0239 num-lanes = <1>;
0240 clocks = <&gateclk 10>;
0241 };
0242
0243 pcie@7,0 {
0244 device_type = "pci";
0245 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
0246 reg = <0x3800 0 0 0 0>;
0247 #address-cells = <3>;
0248 #size-cells = <2>;
0249 #interrupt-cells = <1>;
0250 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0251 0x81000000 0 0 0x81000000 0x7 0 1 0>;
0252 interrupt-map-mask = <0 0 0 0>;
0253 interrupt-map = <0 0 0 0 &mpic 64>;
0254 marvell,pcie-port = <1>;
0255 marvell,pcie-lane = <2>;
0256 num-lanes = <1>;
0257 clocks = <&gateclk 11>;
0258 };
0259
0260 pcie@8,0 {
0261 device_type = "pci";
0262 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
0263 reg = <0x4000 0 0 0 0>;
0264 #address-cells = <3>;
0265 #size-cells = <2>;
0266 #interrupt-cells = <1>;
0267 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0268 0x81000000 0 0 0x81000000 0x8 0 1 0>;
0269 interrupt-map-mask = <0 0 0 0>;
0270 interrupt-map = <0 0 0 0 &mpic 65>;
0271 marvell,pcie-port = <1>;
0272 marvell,pcie-lane = <3>;
0273 num-lanes = <1>;
0274 clocks = <&gateclk 12>;
0275 };
0276
0277 pcie@9,0 {
0278 device_type = "pci";
0279 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
0280 reg = <0x4800 0 0 0 0>;
0281 #address-cells = <3>;
0282 #size-cells = <2>;
0283 #interrupt-cells = <1>;
0284 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0285 0x81000000 0 0 0x81000000 0x9 0 1 0>;
0286 interrupt-map-mask = <0 0 0 0>;
0287 interrupt-map = <0 0 0 0 &mpic 99>;
0288 marvell,pcie-port = <2>;
0289 marvell,pcie-lane = <0>;
0290 num-lanes = <1>;
0291 clocks = <&gateclk 26>;
0292 };
0293
0294 pcie@a,0 {
0295 device_type = "pci";
0296 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
0297 reg = <0x5000 0 0 0 0>;
0298 #address-cells = <3>;
0299 #size-cells = <2>;
0300 #interrupt-cells = <1>;
0301 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0302 0x81000000 0 0 0x81000000 0xa 0 1 0>;
0303 interrupt-map-mask = <0 0 0 0>;
0304 interrupt-map = <0 0 0 0 &mpic 103>;
0305 marvell,pcie-port = <3>;
0306 marvell,pcie-lane = <0>;
0307 num-lanes = <1>;
0308 clocks = <&gateclk 27>;
0309 };
0310 };
