0001 * Mobiveil AXI PCIe Root Port Bridge DT description
0002
0003 Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
0004 has up to 8 outbound and inbound windows for the address translation.
0005
0006 Required properties:
0007 - #address-cells: Address representation for root ports, set to <3>
0008 - #size-cells: Size representation for root ports, set to <2>
0009 - #interrupt-cells: specifies the number of cells needed to encode an
0010 interrupt source. The value must be 1.
0011 - compatible: Should contain "mbvl,gpex40-pcie"
0012 - reg: Should contain PCIe registers location and length
0013 Mandatory:
0014 "config_axi_slave": PCIe controller registers
0015 "csr_axi_slave" : Bridge config registers
0016 Optional:
0017 "gpio_slave" : GPIO registers to control slot power
0018 "apb_csr" : MSI registers
0019
0020 - device_type: must be "pci"
0021 - apio-wins : number of requested apio outbound windows
0022 default 2 outbound windows are configured -
0023 1. Config window
0024 2. Memory window
0025 - ppio-wins : number of requested ppio inbound windows
0026 default 1 inbound memory window is configured.
0027 - bus-range: PCI bus numbers covered
0028 - interrupt-controller: identifies the node as an interrupt controller
0029 - #interrupt-cells: specifies the number of cells needed to encode an
0030 interrupt source. The value must be 1.
0031 - interrupts: The interrupt line of the PCIe controller
0032 last cell of this field is set to 4 to
0033 denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
0034 - interrupt-map-mask,
0035 interrupt-map: standard PCI properties to define the mapping of the
0036 PCI interface to interrupt numbers.
0037 - ranges: ranges for the PCI memory regions (I/O space region is not
0038 supported by hardware)
0039 Please refer to the standard PCI bus binding document for a more
0040 detailed explanation
0041
0042
0043 Example:
0044 ++++++++
0045 pcie0: pcie@a0000000 {
0046 #address-cells = <3>;
0047 #size-cells = <2>;
0048 compatible = "mbvl,gpex40-pcie";
0049 reg = <0xa0000000 0x00001000>,
0050 <0xb0000000 0x00010000>,
0051 <0xff000000 0x00200000>,
0052 <0xb0010000 0x00001000>;
0053 reg-names = "config_axi_slave",
0054 "csr_axi_slave",
0055 "gpio_slave",
0056 "apb_csr";
0057 device_type = "pci";
0058 apio-wins = <2>;
0059 ppio-wins = <1>;
0060 bus-range = <0x00000000 0x000000ff>;
0061 interrupt-controller;
0062 interrupt-parent = <&gic>;
0063 #interrupt-cells = <1>;
0064 interrupts = < 0 89 4 >;
0065 interrupt-map-mask = <0 0 0 7>;
0066 interrupt-map = <0 0 0 0 &pci_express 0>,
0067 <0 0 0 1 &pci_express 1>,
0068 <0 0 0 2 &pci_express 2>,
0069 <0 0 0 3 &pci_express 3>;
0070 ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
0071
0072 };
