0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings
0008
0009 maintainers:
0010 - Daire McNamara <daire.mcnamara@microchip.com>
0011
0012 allOf:
0013 - $ref: /schemas/pci/pci-bus.yaml#
0014 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
0015
0016 properties:
0017 compatible:
0018 const: microchip,pcie-host-1.0 # PolarFire
0019
0020 reg:
0021 maxItems: 2
0022
0023 reg-names:
0024 items:
0025 - const: cfg
0026 - const: apb
0027
0028 interrupts:
0029 minItems: 1
0030 items:
0031 - description: PCIe host controller
0032 - description: builtin MSI controller
0033
0034 interrupt-names:
0035 minItems: 1
0036 items:
0037 - const: pcie
0038 - const: msi
0039
0040 ranges:
0041 maxItems: 1
0042
0043 msi-controller:
0044 description: Identifies the node as an MSI controller.
0045
0046 msi-parent:
0047 description: MSI controller the device is capable of using.
0048
0049 interrupt-controller:
0050 type: object
0051 properties:
0052 '#address-cells':
0053 const: 0
0054
0055 '#interrupt-cells':
0056 const: 1
0057
0058 interrupt-controller: true
0059
0060 required:
0061 - '#address-cells'
0062 - '#interrupt-cells'
0063 - interrupt-controller
0064
0065 additionalProperties: false
0066
0067 required:
0068 - reg
0069 - reg-names
0070 - "#interrupt-cells"
0071 - interrupts
0072 - interrupt-map-mask
0073 - interrupt-map
0074 - msi-controller
0075
0076 unevaluatedProperties: false
0077
0078 examples:
0079 - |
0080 soc {
0081 #address-cells = <2>;
0082 #size-cells = <2>;
0083 pcie0: pcie@2030000000 {
0084 compatible = "microchip,pcie-host-1.0";
0085 reg = <0x0 0x70000000 0x0 0x08000000>,
0086 <0x0 0x43000000 0x0 0x00010000>;
0087 reg-names = "cfg", "apb";
0088 device_type = "pci";
0089 #address-cells = <3>;
0090 #size-cells = <2>;
0091 #interrupt-cells = <1>;
0092 interrupts = <119>;
0093 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
0094 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
0095 <0 0 0 2 &pcie_intc0 1>,
0096 <0 0 0 3 &pcie_intc0 2>,
0097 <0 0 0 4 &pcie_intc0 3>;
0098 interrupt-parent = <&plic0>;
0099 msi-parent = <&pcie0>;
0100 msi-controller;
0101 bus-range = <0x00 0x7f>;
0102 ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
0103 pcie_intc0: interrupt-controller {
0104 #address-cells = <0>;
0105 #interrupt-cells = <1>;
0106 interrupt-controller;
0107 };
0108 };
0109 };
