0001 MediaTek Gen2 PCIe controller
0002
0003 Required properties:
0004 - compatible: Should contain one of the following strings:
0005 "mediatek,mt2701-pcie"
0006 "mediatek,mt2712-pcie"
0007 "mediatek,mt7622-pcie"
0008 "mediatek,mt7623-pcie"
0009 "mediatek,mt7629-pcie"
0010 "airoha,en7523-pcie"
0011 - device_type: Must be "pci"
0012 - reg: Base addresses and lengths of the root ports.
0013 - reg-names: Names of the above areas to use during resource lookup.
0014 - #address-cells: Address representation for root ports (must be 3)
0015 - #size-cells: Size representation for root ports (must be 2)
0016 - clocks: Must contain an entry for each entry in clock-names.
0017 See ../clocks/clock-bindings.txt for details.
0018 - clock-names:
0019 Mandatory entries:
0020 - sys_ckN :transaction layer and data link layer clock
0021 Required entries for MT2701/MT7623:
0022 - free_ck :for reference clock of PCIe subsys
0023 Required entries for MT2712/MT7622:
0024 - ahb_ckN :AHB slave interface operating clock for CSR access and RC
0025 initiated MMIO access
0026 Required entries for MT7622:
0027 - axi_ckN :application layer MMIO channel operating clock
0028 - aux_ckN :pe2_mac_bridge and pe2_mac_core operating clock when
0029 pcie_mac_ck/pcie_pipe_ck is turned off
0030 - obff_ckN :OBFF functional block operating clock
0031 - pipe_ckN :LTSSM and PHY/MAC layer operating clock
0032 where N starting from 0 to one less than the number of root ports.
0033 - phys: List of PHY specifiers (used by generic PHY framework).
0034 - phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
0035 number of PHYs as specified in *phys* property.
0036 - power-domains: A phandle and power domain specifier pair to the power domain
0037 which is responsible for collapsing and restoring power to the peripheral.
0038 - bus-range: Range of bus numbers associated with this controller.
0039 - ranges: Ranges for the PCI memory and I/O regions.
0040
0041 Required properties for MT7623/MT2701:
0042 - #interrupt-cells: Size representation for interrupts (must be 1)
0043 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
0044 Please refer to the standard PCI bus binding document for a more detailed
0045 explanation.
0046 - resets: Must contain an entry for each entry in reset-names.
0047 See ../reset/reset.txt for details.
0048 - reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
0049 number of root ports.
0050
0051 Required properties for MT2712/MT7622/MT7629:
0052 -interrupts: A list of interrupt outputs of the controller, must have one
0053 entry for each PCIe port
0054 - interrupt-names: Must include the following entries:
0055 - "pcie_irq": The interrupt that is asserted when an MSI/INTX is received
0056 - linux,pci-domain: PCI domain ID. Should be unique for each host controller
0057
0058 In addition, the device tree node must have sub-nodes describing each
0059 PCIe port interface, having the following mandatory properties:
0060
0061 Required properties:
0062 - device_type: Must be "pci"
0063 - reg: Only the first four bytes are used to refer to the correct bus number
0064 and device number.
0065 - #address-cells: Must be 3
0066 - #size-cells: Must be 2
0067 - #interrupt-cells: Must be 1
0068 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
0069 Please refer to the standard PCI bus binding document for a more detailed
0070 explanation.
0071 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
0072 property is sufficient.
0073
0074 Examples for MT7623:
0075
0076 hifsys: syscon@1a000000 {
0077 compatible = "mediatek,mt7623-hifsys",
0078 "mediatek,mt2701-hifsys",
0079 "syscon";
0080 reg = <0 0x1a000000 0 0x1000>;
0081 #clock-cells = <1>;
0082 #reset-cells = <1>;
0083 };
0084
0085 pcie: pcie@1a140000 {
0086 compatible = "mediatek,mt7623-pcie";
0087 device_type = "pci";
0088 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
0089 <0 0x1a142000 0 0x1000>, /* Port0 registers */
0090 <0 0x1a143000 0 0x1000>, /* Port1 registers */
0091 <0 0x1a144000 0 0x1000>; /* Port2 registers */
0092 reg-names = "subsys", "port0", "port1", "port2";
0093 #address-cells = <3>;
0094 #size-cells = <2>;
0095 #interrupt-cells = <1>;
0096 interrupt-map-mask = <0xf800 0 0 0>;
0097 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
0098 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
0099 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
0100 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
0101 <&hifsys CLK_HIFSYS_PCIE0>,
0102 <&hifsys CLK_HIFSYS_PCIE1>,
0103 <&hifsys CLK_HIFSYS_PCIE2>;
0104 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
0105 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
0106 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
0107 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
0108 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
0109 phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
0110 <&pcie2_phy PHY_TYPE_PCIE>;
0111 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
0112 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
0113 bus-range = <0x00 0xff>;
0114 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
0115 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
0116
0117 pcie@0,0 {
0118 reg = <0x0000 0 0 0 0>;
0119 #address-cells = <3>;
0120 #size-cells = <2>;
0121 #interrupt-cells = <1>;
0122 interrupt-map-mask = <0 0 0 0>;
0123 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
0124 ranges;
0125 };
0126
0127 pcie@1,0 {
0128 reg = <0x0800 0 0 0 0>;
0129 #address-cells = <3>;
0130 #size-cells = <2>;
0131 #interrupt-cells = <1>;
0132 interrupt-map-mask = <0 0 0 0>;
0133 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
0134 ranges;
0135 };
0136
0137 pcie@2,0 {
0138 reg = <0x1000 0 0 0 0>;
0139 #address-cells = <3>;
0140 #size-cells = <2>;
0141 #interrupt-cells = <1>;
0142 interrupt-map-mask = <0 0 0 0>;
0143 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
0144 ranges;
0145 };
0146 };
0147
0148 Examples for MT2712:
0149
0150 pcie1: pcie@112ff000 {
0151 compatible = "mediatek,mt2712-pcie";
0152 device_type = "pci";
0153 reg = <0 0x112ff000 0 0x1000>;
0154 reg-names = "port1";
0155 linux,pci-domain = <1>;
0156 #address-cells = <3>;
0157 #size-cells = <2>;
0158 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
0159 interrupt-names = "pcie_irq";
0160 clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
0161 <&pericfg CLK_PERI_PCIE1>;
0162 clock-names = "sys_ck1", "ahb_ck1";
0163 phys = <&u3port1 PHY_TYPE_PCIE>;
0164 phy-names = "pcie-phy1";
0165 bus-range = <0x00 0xff>;
0166 ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
0167 status = "disabled";
0168
0169 #interrupt-cells = <1>;
0170 interrupt-map-mask = <0 0 0 7>;
0171 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
0172 <0 0 0 2 &pcie_intc1 1>,
0173 <0 0 0 3 &pcie_intc1 2>,
0174 <0 0 0 4 &pcie_intc1 3>;
0175 pcie_intc1: interrupt-controller {
0176 interrupt-controller;
0177 #address-cells = <0>;
0178 #interrupt-cells = <1>;
0179 };
0180 };
0181
0182 pcie0: pcie@11700000 {
0183 compatible = "mediatek,mt2712-pcie";
0184 device_type = "pci";
0185 reg = <0 0x11700000 0 0x1000>;
0186 reg-names = "port0";
0187 linux,pci-domain = <0>;
0188 #address-cells = <3>;
0189 #size-cells = <2>;
0190 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
0191 interrupt-names = "pcie_irq";
0192 clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
0193 <&pericfg CLK_PERI_PCIE0>;
0194 clock-names = "sys_ck0", "ahb_ck0";
0195 phys = <&u3port0 PHY_TYPE_PCIE>;
0196 phy-names = "pcie-phy0";
0197 bus-range = <0x00 0xff>;
0198 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
0199 status = "disabled";
0200
0201 #interrupt-cells = <1>;
0202 interrupt-map-mask = <0 0 0 7>;
0203 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
0204 <0 0 0 2 &pcie_intc0 1>,
0205 <0 0 0 3 &pcie_intc0 2>,
0206 <0 0 0 4 &pcie_intc0 3>;
0207 pcie_intc0: interrupt-controller {
0208 interrupt-controller;
0209 #address-cells = <0>;
0210 #interrupt-cells = <1>;
0211 };
0212 };
0213
0214 Examples for MT7622:
0215
0216 pcie0: pcie@1a143000 {
0217 compatible = "mediatek,mt7622-pcie";
0218 device_type = "pci";
0219 reg = <0 0x1a143000 0 0x1000>;
0220 reg-names = "port0";
0221 linux,pci-domain = <0>;
0222 #address-cells = <3>;
0223 #size-cells = <2>;
0224 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
0225 interrupt-names = "pcie_irq";
0226 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
0227 <&pciesys CLK_PCIE_P0_AHB_EN>,
0228 <&pciesys CLK_PCIE_P0_AUX_EN>,
0229 <&pciesys CLK_PCIE_P0_AXI_EN>,
0230 <&pciesys CLK_PCIE_P0_OBFF_EN>,
0231 <&pciesys CLK_PCIE_P0_PIPE_EN>;
0232 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
0233 "axi_ck0", "obff_ck0", "pipe_ck0";
0234
0235 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
0236 bus-range = <0x00 0xff>;
0237 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
0238 status = "disabled";
0239
0240 #interrupt-cells = <1>;
0241 interrupt-map-mask = <0 0 0 7>;
0242 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
0243 <0 0 0 2 &pcie_intc0 1>,
0244 <0 0 0 3 &pcie_intc0 2>,
0245 <0 0 0 4 &pcie_intc0 3>;
0246 pcie_intc0: interrupt-controller {
0247 interrupt-controller;
0248 #address-cells = <0>;
0249 #interrupt-cells = <1>;
0250 };
0251 };
0252
0253 pcie1: pcie@1a145000 {
0254 compatible = "mediatek,mt7622-pcie";
0255 device_type = "pci";
0256 reg = <0 0x1a145000 0 0x1000>;
0257 reg-names = "port1";
0258 linux,pci-domain = <1>;
0259 #address-cells = <3>;
0260 #size-cells = <2>;
0261 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
0262 interrupt-names = "pcie_irq";
0263 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
0264 /* designer has connect RC1 with p0_ahb clock */
0265 <&pciesys CLK_PCIE_P0_AHB_EN>,
0266 <&pciesys CLK_PCIE_P1_AUX_EN>,
0267 <&pciesys CLK_PCIE_P1_AXI_EN>,
0268 <&pciesys CLK_PCIE_P1_OBFF_EN>,
0269 <&pciesys CLK_PCIE_P1_PIPE_EN>;
0270 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
0271 "axi_ck1", "obff_ck1", "pipe_ck1";
0272
0273 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
0274 bus-range = <0x00 0xff>;
0275 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
0276 status = "disabled";
0277
0278 #interrupt-cells = <1>;
0279 interrupt-map-mask = <0 0 0 7>;
0280 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
0281 <0 0 0 2 &pcie_intc1 1>,
0282 <0 0 0 3 &pcie_intc1 2>,
0283 <0 0 0 4 &pcie_intc1 3>;
0284 pcie_intc1: interrupt-controller {
0285 interrupt-controller;
0286 #address-cells = <0>;
0287 #interrupt-cells = <1>;
0288 };
0289 };
