bindings/pci/mediatek-pcie-gen3.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Gen3 PCIe controller on MediaTek SoCs
0008
0009 maintainers:
0010   - Jianjun Wang <jianjun.wang@mediatek.com>
0011
0012 description: |+
0013   PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
0014   and compatible with Gen2, Gen1 speed.
0015
0016   This PCIe controller supports up to 256 MSI vectors, the MSI hardware
0017   block diagram is as follows:
0018
0019                     +-----+
0020                     | GIC |
0021                     +-----+
0022                        ^
0023                        |
0024                    port->irq
0025                        |
0026                +-+-+-+-+-+-+-+-+
0027                |0|1|2|3|4|5|6|7| (PCIe intc)
0028                +-+-+-+-+-+-+-+-+
0029                 ^ ^           ^
0030                 | |    ...    |
0031         +-------+ +------+    +-----------+
0032         |                |                |
0033   +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
0034   |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
0035   +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
0036    ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
0037    | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
0038    | |      |  |    | |      |  |    | |      |  |
0039
0040     (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
0041
0042   With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
0043   each set has its own address for MSI message, and supports 32 MSI vectors
0044   to generate interrupt.
0045
0046 allOf:
0047   - $ref: /schemas/pci/pci-bus.yaml#
0048
0049 properties:
0050   compatible:
0051     const: mediatek,mt8192-pcie
0052
0053   reg:
0054     maxItems: 1
0055
0056   reg-names:
0057     items:
0058       - const: pcie-mac
0059
0060   interrupts:
0061     maxItems: 1
0062
0063   ranges:
0064     minItems: 1
0065     maxItems: 8
0066
0067   resets:
0068     minItems: 1
0069     maxItems: 2
0070
0071   reset-names:
0072     minItems: 1
0073     items:
0074       - const: phy
0075       - const: mac
0076
0077   clocks:
0078     maxItems: 6
0079
0080   clock-names:
0081     items:
0082       - const: pl_250m
0083       - const: tl_26m
0084       - const: tl_96m
0085       - const: tl_32k
0086       - const: peri_26m
0087       - const: top_133m
0088
0089   assigned-clocks:
0090     maxItems: 1
0091
0092   assigned-clock-parents:
0093     maxItems: 1
0094
0095   phys:
0096     maxItems: 1
0097
0098   phy-names:
0099     items:
0100       - const: pcie-phy
0101
0102   '#interrupt-cells':
0103     const: 1
0104
0105   interrupt-controller:
0106     description: Interrupt controller node for handling legacy PCI interrupts.
0107     type: object
0108     properties:
0109       '#address-cells':
0110         const: 0
0111       '#interrupt-cells':
0112         const: 1
0113       interrupt-controller: true
0114
0115     required:
0116       - '#address-cells'
0117       - '#interrupt-cells'
0118       - interrupt-controller
0119
0120     additionalProperties: false
0121
0122 required:
0123   - compatible
0124   - reg
0125   - reg-names
0126   - interrupts
0127   - ranges
0128   - clocks
0129   - '#interrupt-cells'
0130   - interrupt-controller
0131
0132 unevaluatedProperties: false
0133
0134 examples:
0135   - |
0136     #include <dt-bindings/interrupt-controller/arm-gic.h>
0137     #include <dt-bindings/interrupt-controller/irq.h>
0138
0139     bus {
0140         #address-cells = <2>;
0141         #size-cells = <2>;
0142
0143         pcie: pcie@11230000 {
0144             compatible = "mediatek,mt8192-pcie";
0145             device_type = "pci";
0146             #address-cells = <3>;
0147             #size-cells = <2>;
0148             reg = <0x00 0x11230000 0x00 0x4000>;
0149             reg-names = "pcie-mac";
0150             interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
0151             bus-range = <0x00 0xff>;
0152             ranges = <0x82000000 0x00 0x12000000 0x00
0153                       0x12000000 0x00 0x1000000>;
0154             clocks = <&infracfg 44>,
0155                      <&infracfg 40>,
0156                      <&infracfg 43>,
0157                      <&infracfg 97>,
0158                      <&infracfg 99>,
0159                      <&infracfg 111>;
0160             clock-names = "pl_250m", "tl_26m", "tl_96m",
0161                           "tl_32k", "peri_26m", "top_133m";
0162             assigned-clocks = <&topckgen 50>;
0163             assigned-clock-parents = <&topckgen 91>;
0164
0165             phys = <&pciephy>;
0166             phy-names = "pcie-phy";
0167
0168             resets = <&infracfg_rst 2>,
0169                      <&infracfg_rst 3>;
0170             reset-names = "phy", "mac";
0171
0172             #interrupt-cells = <1>;
0173             interrupt-map-mask = <0 0 0 0x7>;
0174             interrupt-map = <0 0 0 1 &pcie_intc 0>,
0175                             <0 0 0 2 &pcie_intc 1>,
0176                             <0 0 0 3 &pcie_intc 2>,
0177                             <0 0 0 4 &pcie_intc 3>;
0178             pcie_intc: interrupt-controller {
0179                       #address-cells = <0>;
0180                       #interrupt-cells = <1>;
0181                       interrupt-controller;
0182             };
0183         };
0184     };