0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: MediaTek MT7621 PCIe controller
0008
0009 maintainers:
0010 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
0011
0012 description: |+
0013 MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
0014 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
0015
0016 allOf:
0017 - $ref: /schemas/pci/pci-bus.yaml#
0018
0019 properties:
0020 compatible:
0021 const: mediatek,mt7621-pci
0022
0023 reg:
0024 items:
0025 - description: host-pci bridge registers
0026 - description: pcie port 0 RC control registers
0027 - description: pcie port 1 RC control registers
0028 - description: pcie port 2 RC control registers
0029
0030 ranges:
0031 maxItems: 2
0032
0033 patternProperties:
0034 'pcie@[0-2],0':
0035 type: object
0036 $ref: /schemas/pci/pci-bus.yaml#
0037
0038 properties:
0039 resets:
0040 maxItems: 1
0041
0042 clocks:
0043 maxItems: 1
0044
0045 phys:
0046 maxItems: 1
0047
0048 phy-names:
0049 pattern: '^pcie-phy[0-2]$'
0050
0051 required:
0052 - "#interrupt-cells"
0053 - interrupt-map-mask
0054 - interrupt-map
0055 - resets
0056 - clocks
0057 - phys
0058 - phy-names
0059 - ranges
0060
0061 unevaluatedProperties: false
0062
0063 required:
0064 - compatible
0065 - reg
0066 - ranges
0067 - "#interrupt-cells"
0068 - interrupt-map-mask
0069 - interrupt-map
0070 - reset-gpios
0071
0072 unevaluatedProperties: false
0073
0074 examples:
0075 - |
0076 #include <dt-bindings/gpio/gpio.h>
0077 #include <dt-bindings/interrupt-controller/mips-gic.h>
0078
0079 pcie: pcie@1e140000 {
0080 compatible = "mediatek,mt7621-pci";
0081 reg = <0x1e140000 0x100>,
0082 <0x1e142000 0x100>,
0083 <0x1e143000 0x100>,
0084 <0x1e144000 0x100>;
0085
0086 #address-cells = <3>;
0087 #size-cells = <2>;
0088 pinctrl-names = "default";
0089 pinctrl-0 = <&pcie_pins>;
0090 device_type = "pci";
0091 ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
0092 <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
0093 #interrupt-cells = <1>;
0094 interrupt-map-mask = <0xF800 0 0 0>;
0095 interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
0096 <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
0097 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
0098 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
0099
0100 pcie@0,0 {
0101 reg = <0x0000 0 0 0 0>;
0102 #address-cells = <3>;
0103 #size-cells = <2>;
0104 device_type = "pci";
0105 #interrupt-cells = <1>;
0106 interrupt-map-mask = <0 0 0 0>;
0107 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
0108 resets = <&rstctrl 24>;
0109 clocks = <&clkctrl 24>;
0110 phys = <&pcie0_phy 1>;
0111 phy-names = "pcie-phy0";
0112 ranges;
0113 };
0114
0115 pcie@1,0 {
0116 reg = <0x0800 0 0 0 0>;
0117 #address-cells = <3>;
0118 #size-cells = <2>;
0119 device_type = "pci";
0120 #interrupt-cells = <1>;
0121 interrupt-map-mask = <0 0 0 0>;
0122 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
0123 resets = <&rstctrl 25>;
0124 clocks = <&clkctrl 25>;
0125 phys = <&pcie0_phy 1>;
0126 phy-names = "pcie-phy1";
0127 ranges;
0128 };
0129
0130 pcie@2,0 {
0131 reg = <0x1000 0 0 0 0>;
0132 #address-cells = <3>;
0133 #size-cells = <2>;
0134 device_type = "pci";
0135 #interrupt-cells = <1>;
0136 interrupt-map-mask = <0 0 0 0>;
0137 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
0138 resets = <&rstctrl 26>;
0139 clocks = <&clkctrl 26>;
0140 phys = <&pcie2_phy 0>;
0141 phy-names = "pcie-phy2";
0142 ranges;
0143 };
0144 };
0145 ...
