0001 NXP Layerscape PCIe Gen4 controller
0002
0003 This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
0004 the common properties defined in mobiveil-pcie.txt.
0005
0006 Required properties:
0007 - compatible: should contain the platform identifier such as:
0008 "fsl,lx2160a-pcie"
0009 - reg: base addresses and lengths of the PCIe controller register blocks.
0010 "csr_axi_slave": Bridge config registers
0011 "config_axi_slave": PCIe controller registers
0012 - interrupts: A list of interrupt outputs of the controller. Must contain an
0013 entry for each entry in the interrupt-names property.
0014 - interrupt-names: It could include the following entries:
0015 "intr": The interrupt that is asserted for controller interrupts
0016 "aer": Asserted for aer interrupt when chip support the aer interrupt with
0017 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
0018 "pme": Asserted for pme interrupt when chip support the pme interrupt with
0019 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
0020 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
0021 of the data transferred from/to the IP block. This can avoid the software
0022 cache flush/invalid actions, and improve the performance significantly.
0023 - msi-parent : See the generic MSI binding described in
0024 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
0025
0026 Example:
0027
0028 pcie@3400000 {
0029 compatible = "fsl,lx2160a-pcie";
0030 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0031 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
0032 reg-names = "csr_axi_slave", "config_axi_slave";
0033 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
0034 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
0035 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
0036 interrupt-names = "aer", "pme", "intr";
0037 #address-cells = <3>;
0038 #size-cells = <2>;
0039 device_type = "pci";
0040 apio-wins = <8>;
0041 ppio-wins = <8>;
0042 dma-coherent;
0043 bus-range = <0x0 0xff>;
0044 msi-parent = <&its>;
0045 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
0046 #interrupt-cells = <1>;
0047 interrupt-map-mask = <0 0 0 7>;
0048 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0049 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
0050 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
0051 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
0052 };
