0001 Freescale Layerscape PCIe controller
0002
0003 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
0004 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
0005
0006 This controller derives its clocks from the Reset Configuration Word (RCW)
0007 which is used to describe the PLL settings at the time of chip-reset.
0008
0009 Also as per the available Reference Manuals, there is no specific 'version'
0010 register available in the Freescale PCIe controller register set,
0011 which can allow determining the underlying DesignWare PCIe controller version
0012 information.
0013
0014 Required properties:
0015 - compatible: should contain the platform identifier such as:
0016 RC mode:
0017 "fsl,ls1021a-pcie"
0018 "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
0019 "fsl,ls2088a-pcie"
0020 "fsl,ls1088a-pcie"
0021 "fsl,ls1046a-pcie"
0022 "fsl,ls1043a-pcie"
0023 "fsl,ls1012a-pcie"
0024 "fsl,ls1028a-pcie"
0025 EP mode:
0026 "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep"
0027 "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
0028 "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep"
0029 "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep"
0030 "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep"
0031 - reg: base addresses and lengths of the PCIe controller register blocks.
0032 - interrupts: A list of interrupt outputs of the controller. Must contain an
0033 entry for each entry in the interrupt-names property.
0034 - interrupt-names: It could include the following entries:
0035 "aer": Used for interrupt line which reports AER events when
0036 non MSI/MSI-X/INTx mode is used
0037 "pme": Used for interrupt line which reports PME events when
0038 non MSI/MSI-X/INTx mode is used
0039 "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a)
0040 which has a single interrupt line for miscellaneous controller
0041 events(could include AER and PME events).
0042 - fsl,pcie-scfg: Must include two entries.
0043 The first entry must be a link to the SCFG device node
0044 The second entry is the physical PCIe controller index starting from '0'.
0045 This is used to get SCFG PEXN registers
0046 - dma-coherent: Indicates that the hardware IP block can ensure the coherency
0047 of the data transferred from/to the IP block. This can avoid the software
0048 cache flush/invalid actions, and improve the performance significantly.
0049
0050 Optional properties:
0051 - big-endian: If the PEX_LUT and PF register block is in big-endian, specify
0052 this property.
0053
0054 Example:
0055
0056 pcie@3400000 {
0057 compatible = "fsl,ls1088a-pcie";
0058 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
0059 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
0060 reg-names = "regs", "config";
0061 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
0062 interrupt-names = "aer";
0063 #address-cells = <3>;
0064 #size-cells = <2>;
0065 device_type = "pci";
0066 dma-coherent;
0067 num-viewport = <256>;
0068 bus-range = <0x0 0xff>;
0069 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
0070 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
0071 msi-parent = <&its>;
0072 #interrupt-cells = <1>;
0073 interrupt-map-mask = <0 0 0 7>;
0074 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
0075 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
0076 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
0077 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
0078 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
0079 };
