bindings/pci/intel-gw-pcie.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/intel-gw-pcie.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: PCIe RC controller on Intel Gateway SoCs
0008
0009 maintainers:
0010   - Rahul Tanwar <rtanwar@maxlinear.com>
0011
0012 select:
0013   properties:
0014     compatible:
0015       contains:
0016         const: intel,lgm-pcie
0017   required:
0018     - compatible
0019
0020 allOf:
0021   - $ref: /schemas/pci/snps,dw-pcie.yaml#
0022
0023 properties:
0024   compatible:
0025     items:
0026       - const: intel,lgm-pcie
0027       - const: snps,dw-pcie
0028
0029   reg:
0030     items:
0031       - description: Controller control and status registers.
0032       - description: PCIe configuration registers.
0033       - description: Controller application registers.
0034
0035   reg-names:
0036     items:
0037       - const: dbi
0038       - const: config
0039       - const: app
0040
0041   ranges:
0042     maxItems: 1
0043
0044   resets:
0045     maxItems: 1
0046
0047   clocks:
0048     maxItems: 1
0049
0050   phys:
0051     maxItems: 1
0052
0053   phy-names:
0054     const: pcie
0055
0056   reset-gpios:
0057     maxItems: 1
0058
0059   num-lanes:
0060     maximum: 2
0061
0062   max-link-speed:
0063     enum: [1, 2, 3, 4]
0064     default: 1
0065
0066   reset-assert-ms:
0067     description: |
0068       Delay after asserting reset to the PCIe device.
0069     maximum: 500
0070     default: 100
0071
0072 required:
0073   - compatible
0074   - reg
0075   - reg-names
0076   - ranges
0077   - resets
0078   - clocks
0079   - phys
0080   - phy-names
0081   - reset-gpios
0082   - '#interrupt-cells'
0083   - interrupt-map
0084   - interrupt-map-mask
0085
0086 unevaluatedProperties: false
0087
0088 examples:
0089   - |
0090     #include <dt-bindings/gpio/gpio.h>
0091     pcie10: pcie@d0e00000 {
0092       compatible = "intel,lgm-pcie", "snps,dw-pcie";
0093       device_type = "pci";
0094       #address-cells = <3>;
0095       #size-cells = <2>;
0096       reg = <0xd0e00000 0x1000>,
0097             <0xd2000000 0x800000>,
0098             <0xd0a41000 0x1000>;
0099       reg-names = "dbi", "config", "app";
0100       linux,pci-domain = <0>;
0101       max-link-speed = <4>;
0102       bus-range = <0x00 0x08>;
0103       #interrupt-cells = <1>;
0104       interrupt-map-mask = <0 0 0 0x7>;
0105       interrupt-map = <0 0 0 1 &ioapic1 27 1>,
0106                       <0 0 0 2 &ioapic1 28 1>,
0107                       <0 0 0 3 &ioapic1 29 1>,
0108                       <0 0 0 4 &ioapic1 30 1>;
0109       ranges = <0x02000000 0 0xd4000000 0xd4000000 0 0x04000000>;
0110       resets = <&rcu0 0x50 0>;
0111       clocks = <&cgu0 120>;
0112       phys = <&cb0phy0>;
0113       phy-names = "pcie";
0114       reset-assert-ms = <500>;
0115       reset-gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
0116       num-lanes = <2>;
0117     };