0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/pci/intel,keembay-pcie-ep.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Intel Keem Bay PCIe controller Endpoint mode
0008
0009 maintainers:
0010 - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
0011 - Srikanth Thokala <srikanth.thokala@intel.com>
0012
0013 properties:
0014 compatible:
0015 const: intel,keembay-pcie-ep
0016
0017 reg:
0018 maxItems: 5
0019
0020 reg-names:
0021 items:
0022 - const: dbi
0023 - const: dbi2
0024 - const: atu
0025 - const: addr_space
0026 - const: apb
0027
0028 interrupts:
0029 maxItems: 4
0030
0031 interrupt-names:
0032 items:
0033 - const: pcie
0034 - const: pcie_ev
0035 - const: pcie_err
0036 - const: pcie_mem_access
0037
0038 num-lanes:
0039 description: Number of lanes to use.
0040 enum: [ 1, 2 ]
0041
0042 required:
0043 - compatible
0044 - reg
0045 - reg-names
0046 - interrupts
0047 - interrupt-names
0048
0049 additionalProperties: false
0050
0051 examples:
0052 - |
0053 #include <dt-bindings/interrupt-controller/arm-gic.h>
0054 #include <dt-bindings/interrupt-controller/irq.h>
0055 pcie-ep@37000000 {
0056 compatible = "intel,keembay-pcie-ep";
0057 reg = <0x37000000 0x00001000>,
0058 <0x37100000 0x00001000>,
0059 <0x37300000 0x00001000>,
0060 <0x36000000 0x01000000>,
0061 <0x37800000 0x00000200>;
0062 reg-names = "dbi", "dbi2", "atu", "addr_space", "apb";
0063 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
0064 <GIC_SPI 108 IRQ_TYPE_EDGE_RISING>,
0065 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
0066 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
0067 interrupt-names = "pcie", "pcie_ev", "pcie_err", "pcie_mem_access";
0068 num-lanes = <2>;
0069 };
