0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Generic PCI host controller
0008
0009 maintainers:
0010 - Will Deacon <will@kernel.org>
0011
0012 description: |
0013 Firmware-initialised PCI host controllers and PCI emulations, such as the
0014 virtio-pci implementations found in kvmtool and other para-virtualised
0015 systems, do not require driver support for complexities such as regulator
0016 and clock management. In fact, the controller may not even require the
0017 configuration of a control interface by the operating system, instead
0018 presenting a set of fixed windows describing a subset of IO, Memory and
0019 Configuration Spaces.
0020
0021 Configuration Space is assumed to be memory-mapped (as opposed to being
0022 accessed via an ioport) and laid out with a direct correspondence to the
0023 geography of a PCI bus address by concatenating the various components to
0024 form an offset.
0025
0026 For CAM, this 24-bit offset is:
0027
0028 cfg_offset(bus, device, function, register) =
0029 bus << 16 | device << 11 | function << 8 | register
0030
0031 While ECAM extends this by 4 bits to accommodate 4k of function space:
0032
0033 cfg_offset(bus, device, function, register) =
0034 bus << 20 | device << 15 | function << 12 | register
0035
0036 properties:
0037 compatible:
0038 description: Depends on the layout of configuration space (CAM vs ECAM
0039 respectively). May also have more specific compatibles.
0040 oneOf:
0041 - description:
0042 PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
0043 items:
0044 - const: arm,juno-r1-pcie
0045 - const: plda,xpressrich3-axi
0046 - const: pci-host-ecam-generic
0047 - description: |
0048 ThunderX PCI host controller for pass-1.x silicon
0049
0050 Firmware-initialized PCI host controller to on-chip devices found on
0051 some Cavium ThunderX processors. These devices have ECAM-based config
0052 access, but the BARs are all at fixed addresses. We handle the fixed
0053 addresses by synthesizing Enhanced Allocation (EA) capabilities for
0054 these devices.
0055 const: cavium,pci-host-thunder-ecam
0056 - description:
0057 Cavium ThunderX PEM firmware-initialized PCIe host controller
0058 const: cavium,pci-host-thunder-pem
0059 - description:
0060 HiSilicon Hip06/Hip07 PCIe host bridge in almost-ECAM mode. Some
0061 firmware places the host controller in a mode where it is ECAM
0062 compliant for all devices other than the root complex.
0063 enum:
0064 - hisilicon,hip06-pcie-ecam
0065 - hisilicon,hip07-pcie-ecam
0066 - description: |
0067 In some cases, firmware may already have configured the Synopsys
0068 DesignWare PCIe controller in RC mode with static ATU window mappings
0069 that cover all config, MMIO and I/O spaces in a [mostly] ECAM
0070 compatible fashion. In this case, there is no need for the OS to
0071 perform any low level setup of clocks, PHYs or device registers, nor
0072 is there any reason for the driver to reconfigure ATU windows for
0073 config and/or IO space accesses at runtime.
0074
0075 In cases where the IP was synthesized with a minimum ATU window size
0076 of 64 KB, it cannot be supported by the generic ECAM driver, because
0077 it requires special config space accessors that filter accesses to
0078 device #1 and beyond on the first bus.
0079 items:
0080 - enum:
0081 - marvell,armada8k-pcie-ecam
0082 - socionext,synquacer-pcie-ecam
0083 - const: snps,dw-pcie-ecam
0084 - description:
0085 CAM or ECAM compliant PCI host controllers without any quirks
0086 enum:
0087 - pci-host-cam-generic
0088 - pci-host-ecam-generic
0089
0090 reg:
0091 description:
0092 The Configuration Space base address and size, as accessed from the parent
0093 bus. The base address corresponds to the first bus in the "bus-range"
0094 property. If no "bus-range" is specified, this will be bus 0 (the
0095 default). Some host controllers have a 2nd non-compliant address range,
0096 so 2 entries are allowed.
0097 minItems: 1
0098 maxItems: 2
0099
0100 ranges:
0101 description:
0102 As described in IEEE Std 1275-1994, but must provide at least a
0103 definition of non-prefetchable memory. One or both of prefetchable Memory
0104 and IO Space may also be provided.
0105 minItems: 1
0106 maxItems: 3
0107
0108 dma-coherent: true
0109 iommu-map: true
0110 iommu-map-mask: true
0111 msi-parent: true
0112
0113 required:
0114 - compatible
0115 - reg
0116 - ranges
0117
0118 allOf:
0119 - $ref: /schemas/pci/pci-bus.yaml#
0120 - if:
0121 properties:
0122 compatible:
0123 contains:
0124 const: arm,juno-r1-pcie
0125 then:
0126 required:
0127 - dma-coherent
0128
0129 - if:
0130 properties:
0131 compatible:
0132 not:
0133 contains:
0134 enum:
0135 - cavium,pci-host-thunder-pem
0136 - hisilicon,hip06-pcie-ecam
0137 - hisilicon,hip07-pcie-ecam
0138 then:
0139 properties:
0140 reg:
0141 maxItems: 1
0142
0143 unevaluatedProperties: false
0144
0145 examples:
0146 - |
0147
0148 bus {
0149 #address-cells = <2>;
0150 #size-cells = <2>;
0151 pcie@40000000 {
0152 compatible = "pci-host-cam-generic";
0153 device_type = "pci";
0154 #address-cells = <3>;
0155 #size-cells = <2>;
0156 bus-range = <0x0 0x1>;
0157
0158 // CPU_PHYSICAL(2) SIZE(2)
0159 reg = <0x0 0x40000000 0x0 0x1000000>;
0160
0161 // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2)
0162 ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
0163 <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
0164
0165 #interrupt-cells = <0x1>;
0166
0167 // PCI_DEVICE(3) INT#(1) CONTROLLER(PHANDLE) CONTROLLER_DATA(3)
0168 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
0169 < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
0170 <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
0171 <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
0172
0173 // PCI_DEVICE(3) INT#(1)
0174 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
0175 };
0176 };
0177 ...
