0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Freescale i.MX6 PCIe host controller
0008
0009 maintainers:
0010 - Lucas Stach <l.stach@pengutronix.de>
0011 - Richard Zhu <hongxing.zhu@nxp.com>
0012
0013 description: |+
0014 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
0015 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
0016
0017 allOf:
0018 - $ref: /schemas/pci/snps,dw-pcie.yaml#
0019
0020 properties:
0021 compatible:
0022 enum:
0023 - fsl,imx6q-pcie
0024 - fsl,imx6sx-pcie
0025 - fsl,imx6qp-pcie
0026 - fsl,imx7d-pcie
0027 - fsl,imx8mq-pcie
0028 - fsl,imx8mm-pcie
0029 - fsl,imx8mp-pcie
0030
0031 reg:
0032 items:
0033 - description: Data Bus Interface (DBI) registers.
0034 - description: PCIe configuration space region.
0035
0036 reg-names:
0037 items:
0038 - const: dbi
0039 - const: config
0040
0041 interrupts:
0042 items:
0043 - description: builtin MSI controller.
0044
0045 interrupt-names:
0046 items:
0047 - const: msi
0048
0049 clocks:
0050 minItems: 3
0051 items:
0052 - description: PCIe bridge clock.
0053 - description: PCIe bus clock.
0054 - description: PCIe PHY clock.
0055 - description: Additional required clock entry for imx6sx-pcie,
0056 imx8mq-pcie.
0057
0058 clock-names:
0059 minItems: 3
0060 items:
0061 - const: pcie
0062 - const: pcie_bus
0063 - const: pcie_phy
0064 - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
0065
0066 num-lanes:
0067 const: 1
0068
0069 fsl,imx7d-pcie-phy:
0070 $ref: /schemas/types.yaml#/definitions/phandle
0071 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
0072 required properties for imx7d-pcie and imx8mq-pcie.
0073
0074 power-domains:
0075 items:
0076 - description: The phandle pointing to the DISPLAY domain for
0077 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
0078 imx8mq-pcie.
0079 - description: The phandle pointing to the PCIE_PHY power domains
0080 for imx6sx-pcie.
0081
0082 power-domain-names:
0083 items:
0084 - const: pcie
0085 - const: pcie_phy
0086
0087 resets:
0088 maxItems: 3
0089 description: Phandles to PCIe-related reset lines exposed by SRC
0090 IP block. Additional required by imx7d-pcie and imx8mq-pcie.
0091
0092 reset-names:
0093 items:
0094 - const: pciephy
0095 - const: apps
0096 - const: turnoff
0097
0098 fsl,tx-deemph-gen1:
0099 description: Gen1 De-emphasis value (optional required).
0100 $ref: /schemas/types.yaml#/definitions/uint32
0101 default: 0
0102
0103 fsl,tx-deemph-gen2-3p5db:
0104 description: Gen2 (3.5db) De-emphasis value (optional required).
0105 $ref: /schemas/types.yaml#/definitions/uint32
0106 default: 0
0107
0108 fsl,tx-deemph-gen2-6db:
0109 description: Gen2 (6db) De-emphasis value (optional required).
0110 $ref: /schemas/types.yaml#/definitions/uint32
0111 default: 20
0112
0113 fsl,tx-swing-full:
0114 description: Gen2 TX SWING FULL value (optional required).
0115 $ref: /schemas/types.yaml#/definitions/uint32
0116 default: 127
0117
0118 fsl,tx-swing-low:
0119 description: TX launch amplitude swing_low value (optional required).
0120 $ref: /schemas/types.yaml#/definitions/uint32
0121 default: 127
0122
0123 fsl,max-link-speed:
0124 description: Specify PCI Gen for link capability (optional required).
0125 Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
0126 requirements and thus for gen2 capability a gen2 compliant clock
0127 generator should be used and configured.
0128 $ref: /schemas/types.yaml#/definitions/uint32
0129 enum: [1, 2, 3, 4]
0130 default: 1
0131
0132 phys:
0133 maxItems: 1
0134
0135 phy-names:
0136 const: pcie-phy
0137
0138 reset-gpio:
0139 description: Should specify the GPIO for controlling the PCI bus device
0140 reset signal. It's not polarity aware and defaults to active-low reset
0141 sequence (L=reset state, H=operation state) (optional required).
0142
0143 reset-gpio-active-high:
0144 description: If present then the reset sequence using the GPIO
0145 specified in the "reset-gpio" property is reversed (H=reset state,
0146 L=operation state) (optional required).
0147 type: boolean
0148
0149 vpcie-supply:
0150 description: Should specify the regulator in charge of PCIe port power.
0151 The regulator will be enabled when initializing the PCIe host and
0152 disabled either as part of the init process or when shutting down
0153 the host (optional required).
0154
0155 vph-supply:
0156 description: Should specify the regulator in charge of VPH one of
0157 the three PCIe PHY powers. This regulator can be supplied by both
0158 1.8v and 3.3v voltage supplies (optional required).
0159
0160 required:
0161 - compatible
0162 - reg
0163 - reg-names
0164 - "#address-cells"
0165 - "#size-cells"
0166 - device_type
0167 - bus-range
0168 - ranges
0169 - num-lanes
0170 - interrupts
0171 - interrupt-names
0172 - "#interrupt-cells"
0173 - interrupt-map-mask
0174 - interrupt-map
0175 - clocks
0176 - clock-names
0177
0178 unevaluatedProperties: false
0179
0180 examples:
0181 - |
0182 #include <dt-bindings/clock/imx6qdl-clock.h>
0183 #include <dt-bindings/interrupt-controller/arm-gic.h>
0184
0185 pcie: pcie@1ffc000 {
0186 compatible = "fsl,imx6q-pcie";
0187 reg = <0x01ffc000 0x04000>,
0188 <0x01f00000 0x80000>;
0189 reg-names = "dbi", "config";
0190 #address-cells = <3>;
0191 #size-cells = <2>;
0192 device_type = "pci";
0193 bus-range = <0x00 0xff>;
0194 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>,
0195 <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
0196 num-lanes = <1>;
0197 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0198 interrupt-names = "msi";
0199 #interrupt-cells = <1>;
0200 interrupt-map-mask = <0 0 0 0x7>;
0201 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
0202 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
0203 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
0204 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
0205 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
0206 <&clks IMX6QDL_CLK_LVDS1_GATE>,
0207 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
0208 clock-names = "pcie", "pcie_bus", "pcie_phy";
0209 };
0210 ...
